Digital Systems Testing using Fastscan

Instructions for using FastScan in RISE Lab

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  1. Setting up the environment variables

  2. Check for the required files

  3. Using FastScan for Combinational Circuits

  4. Handling Sequential Circuits

Setting up the environment variables

Create a folder called example1

There are two environment variables that need to be set before using the testing tools from RISE lab. These are:

A shell script that sets up these environment variables can be obtained here. Download this file to example1 folder and type “source” command to setup the variables.

Check whether the environment variables have been properly set by using the env command

Alternately, you can update your .bashrc file with the contents of The .bashrc file is located in your home folder. If such a file does not exist, simply create one and update it.

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Check for required files

  1. In order to use FastScan, we need a gate-level netlist of the circuit for which tests are desired. For this demo, the C17 circuit (from ISCAS benchmark suite) is used. C17 can be obtained here.

  2. The entire suite of ISCAS benchmark circuits can be downloaded from here. Note that circuits of the form c*.v and s*.v are combinational circuits and sequential circuits respectively.

  3. FastScan needs to be provided with an ATPG library file. FastScan uses information from this file during fault simulation. A sample ATPG library file can be downloaded from here. You can open this ATPG file using an ASCII file editor (such as Vim) and explore the contents of the file.

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Using FastScan for Combinational Circuits

Invoke FastScan from the prompt.

This starts the graphical user interface of FastScan.

Click on Browse... button corresponding to Design : and navigate to the folder containing c17.v file. Select it and then click on OK. Ensure that the Format : tab is set to Verilog. Click on Browse... corresponding to ATPG Library : and navigate to the folder containing the file called atpg and select it and then click OK

Click on Invoke FastScan button. This should bring up the following two screens shown below.

Click on Done With Setup button. Clicking this button brings up the Session Purpose window.

Click on Pattern Generation button. Clicking this button brings up the FastScan Control Panel.

Click on Fault Universe box and select Typical from the pop-up window. Next, click on Pattern Source box and select Typical settings.

Click on Test Generation box.

Click on Run with Existing Settings. This will make FastScan to generate tests for the combinational circuit, (i.e. c17.v in our case) and display the report.

Select Save Patterns... from the list on the right-hand side menu. Ensure that Save the Pattern Set to a File is switched on. Select appropriate filename to store the generated test pattern (i.e. c17.test in our case). Ensure that pattern format is set to ascii and click on OK.

Click on Done With Pattern Generation from the FastScan Control Panel. Then select Exit from the pop-up window. Congratulations! You have now successfully generated a test for the ISCAS c17 circuit using FastScan. Any ASCII file editor (like vim) can be used to open and study the contents of the test file c17.test

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Handling SequentialCircuits

Test generation for sequential circuits is slightly more involved than combinational circuits as scan cell(s) are to be identified and scan-chain(s) are to be stitched before we can invoke FastScan. These steps are automatically done by a tool called DFTAdvisor. A quick-start guide on how to use DFTAdvisor and FastScan for sequential circuits is available here.

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Digital Systems Testing Using FastScan
Last Updated on :September 23
, 2009
Web Page Created by Vasanth K Ramesh
IIT Madras, Chennai -