B.Tech - Degree Awarded

S.No Photo Thesis Title E-mail Id Current Position
1 Annamalai Muthukaruppan, A Novel Approach To Placement and Routing Problems for Field Programmable Gate Arrays, 2003. amuthu23@hotmail.com
2 S. Suresh, Novel Partitioning and Synthesis Techniques for Reconfigurable Architectures, 2003. suresh_12may@yahoo.com
3 Ganesh Venkatesh, Agile Hardware Architecture based on FPGAs and Partitioning Algorithms for FPGAs, 2004. ganeshv147@yahoo.co.in
4 A. Manoj Kumar, Technology Mapping for Heterogeneous FPGAs with Embedded Memory Arrays, 2004. amk_141@yahoo.co.in
5 Aditya S. Ramani, On the Testing of LUTs in SRAM based FPGAs, 2004. aditya82@gmail.com
6 Amol Jitendra Mupid, Pseudo Online Methodologies for Interconnects and Dedicated Clock Routing Lines of FPGAs, 2004. amolmupid@yahoo.com
7 P. Pratibha, An Enhanced Evolutionary Approach to Spatial Partitioning for Reconfigurable Environments, 2004. pratibha_iitm@rediffmail.com
8 B. Jayaram, Reconvergence Analysis for Efficiently Handling Hard Problems in CAD for VLSI Design, 2004. bobba@cs.wisc.edu
9 Vikram Chandrasekhar, Single Event upsets in SRAM- Based FPGAs, 2005. cvikram_iitm@yahoo.com
10 M. Sashikant, Novel Approaches for Logic Area Reduction in FPGAs, 2005.
11 Rudresh Rajan Singh, Implementation of a Resource Efficient Architecture for Montgomery Modular Multiplication and RSA Modular Exponentiation on a Reconfigurable Logic, 2005.
12 V. Anirudh, A Tool for Implementing Globally Asynchronous, Locally Synchronous (GALS) Systems, 2005. anirudhvr@gmail.com
13 R. Pradeep, Agile Co-processor Architecture, 2005. pradeeprama@gmail.com Component Design Engineer @ Intel
14 E. Sivasoumya, Placement and Routing of 3D-FPGA using Reinforcement Learning and Support Vector machine, 2005. reachme12@rediffmail.com
15 Sumit Singhal, Globally Asynchronous Locally Synchronous x86 Decoder, May 2006. somy.singhal@gmail.com
16 Santhosh A.Navale, Implementation of JPEG Encoder using GALS Methodology, May 2006. santosh.iitm2002@gmail.com
17 Piyush Kaushal, Analysis of crosstalk in DSM Technology devices, and Global routing algorithm for X Architecture, May 2006. kaushal.piyush@gmail.com Ebay
18 Neelamani Kumar, An Integer Linear Programming Approach To Solve The Global Routing Problem For The X-Architecture, May 2006. neelmari.kumar@gmail.com
19 Ankur Verma, Formalization of an Automatic Assembly Program Generator for Functional Verification and Testing of Assembly Based Architectures, May 2006. ankur.av@gmail.com Associate Member of Technical staff
20 V.Muralidaran, Mitigating Soft Errors in SRAM-based FPGAs using Redundancy Techniques, May 2006. mdaran15@gmail.com
21 Vishal Gupta, Minimizing Crosstalk in On-Chip Buses Using Temporal Redundancy, May 2006. vishalgupta.cse@gmail.com
22 Karthik Gururaj, Generating Power Virus for Combinational CMOS Circuits, May 2006. gururaj.karthik@gmail.com
23 Sudheendra Vijayanarasimhan, A Study of the Memory Performance of Systems, May 2006. svnaras@gmail.com
24 Siva Kumar Sastry Hari, Automatic Constraint based Test Generation Using Behavioral HDL MOdels, May 2007. siva.hari@gmail.com
25 Vishnu Vardhan Reddy Konda, Test Generation for Peak Power Dissipation Using Behavioral Models of Circuits, May 2007. vishnu.iitm@gmail.com
26 Nizar M, Hardware implementation of Queuing and Scheduling module of a network processor, June 2007. nizar.mpn@gmail.com
27 Gaurav Jain, Packet Classification Module for Packet Processing Applications, May 2007. gauravjain.iitm@gmail.com
28 Sandeep Raju T, Reassembly Module for Packet Processing Applications, May 2007. tsandeepraju@gmail.com MBA
29 George Kurian, A Holistic Approach to Scalable Transactional Memory, May 2008. georgekurian.086@gmail.com
30 Arslan Aziz, Implementation of SPIN Protocol on TelosB Platform, May 2008. arslan.aziz7@gmail.com Lead Consultant - Public Policy
31 Abhishek Chanani, Implementation of SMAC protocol on TelosB Platform, May 2008. achanani@gmail.com
32 Amit Gera, Design for Diagnosability, May 2008. amitgeraiitm@gmail.com
33 Vivek Seshadri, Logic Optimization Using Technology Mapping and Resynthesis, May 2009. vseshadr@cs.cmu.edu
34 Chakilam Vamshi Anand, VLSI Implementation of Motion Vector Recovery Algorithms for H.264 based Video Codecs, May 2009. vamshianand@gmail.com
35 M. Nanda Kishore, CUDA Implementation of Lagrangian Interpolation for Motion Vector Recovery in H.264 Video Streams, June 2009. moravapalli.nandu@gmail.com Senior Associate
36 G. Bhargava Reddy, CUDA Implementation of Motion Vector Recovery Using Newton Polynomial Interpolation in H.264 Videos, June 2009. bhargavareddy.g@gmail.com CPU Architecture team, Intel
37 Tummala Rajesh, Motion Vector Recovery for Real-time H.264 Video Streams, June 2009. trajeshreddy@gmail.com Bank of America, Hyderabad
38 Vimalkumar Jeyakumar, A Boolean Satisfiability based approach for the Power Virus problem, June 2009. j.vimal@gmail.com PhD
39 Prabhat Jain, Performance evaluation of Hardware Transactional memory System, May 2010. yoprabhat1@yahoo.com
40 Kurra Srinivas, Enabling efficient compilation of CUDA kernel onto FPGAs, June 2010. thavuryasrinu@gmail.com
41 Immanel Ilavarasan.T, Minimizing Collisions in Accessing Micro- Architectural Structures, 2011. immanuel.ilavarasan@gmail.com
42 Suvinay Subramanian, Systematic Illegal State Identification for Pseudo- Functional Testing, 2011. suvinay@smail.iitm.ac.in PhD
43 Avinash Verma, High Level Synthesis using Assignement Decision Diagrams, May 2014.
44 Pavan Kumar Reddy, High Level Synthesis using Assignment Decision Diagrams, May 2014.
45 Hari Prasad S R, Development of a CC2531 Sniffer on SABRE-lite Platform, May 2014.
46 P. Sai Bhushan, Remote structural health monitoring using wireless sensor motes, May 2014.
47 Vikram Ganapathineedi, Instruction Set Simulator for RISC V, May 2015.
48 B. Vishnu Bhargav, Automatic Assembly Program Generator for RISC V, May 2015.
49 Abhishek Mikkilineni, A method for Power Aware Compilation: RISC-V Instruction Set Architecture, May 2015. abhi4sunny2@gmail.com Device Engineer, SanDisk Device Design Centre Pvt Ltd, Bangalore
50 Sai Ashish Moningi, A method for Power Aware Compilation: RISC-V Instruction Set Architecture, May 2015.
51 Aditya Veluri, A Method for Power Aware Compilation: RISC V Instruction Set Architecture - III, May 2015.
52 Kabir Bansod, Porting Contiki to New Platforms, May 2015.
53 Botcha Prithvi Raj, Hybrid cryptography for encryption and secure voice transmission, May 2016.
54 B Harendra Prasad, Reuse Cache with Conventional Higher-Level Cache for Improving Performance, May 2016.
55 Ashish Gondimalla, Study of P4 Language, April 2016.
56 B V S Kavya Sree, Verification of e-class processor based on RISC-V ISA, May 2016.
57 Bodanki Neel Kumar, A Three-Path Fused Multiply-Add Algorithm For Floating Point Numbers, May 2017
58 N Kranthi Tej, Genode on Secure Tablet, May 2017
59 J Prannoy Noel, Mapping A Spiking Neural Network(SNN) to Truenorth Chip, May 2017
60 Guttula Shanmukha Chaitanya, Congestion Aware Multicast Packet Switched Static Routing Algorithm for 2D Torus based Network on Chip, May 2017