Completed MS

S.No Photo Thesis Title E-mail Id Current Position
1 L. Kalyan Kumar, Pseudo Online Testing Methodologies for Various Components of Field Programmable Gate Arrays, 2003.
2 Siva Nageswara Rao Borra, Partitioning, Placement and Routing Algorithms for Field Programmable Gate Arrays, 2003.
3 K Uday Bhaskar, Automatic Assembly Program Generation for functional Verification and Testing of Processor - Based Architectures, 2006.
4 A Pavan Kumar, A WMPCA-based Face Recognition System on Programmable Chip, 2006 (Jointly with Dr. Sukhendu Das). CAD Engineer
5 Chakka Siva Sai Prasanna, An Area-Time Efficient VLSI Architecture for Eigenface-based Recognition System, 2006 (Jointly with Dr. N. Sudha).
6 Vivek Garg, Boolean Function Generation based Reconfigurable Architectures and Associated Packing Techniques, 2006.
7 E. Syama Sundara Reddy, Novel CLB Architectures and Techniques to Mitigate SEU Faults in SRAM-based FPGAs, 2007. Senior Software Engineer @ Xilinx
8 J. Lavanya, On Test and Diagnostic Methodologies for Nanometer Technologies, 2010.
9 Gomathi Rajan, Development of an Economic High Performance Storage Solution, 2010, MS (Entrepreneurship) - Jointly with Dr. Thillairajan, Department of Management Studies.
10 Kunal K. Korgaonkar, Reconstructing Transactional Memory: Fast Unbound Conflict Detection and Conflict-Graph based Contention Management, 2011.
11 R. Karthik Raghavan, ROSY: Exploring Life After Microarchitectural Death, 2011.
12 Anish Kumar, Network-on-Chips.
13 V. Ashwin, Synthesis techniques for Reversible circuits (jointly with Dr. R. Manivasakan).
14 Pawan Kumar, Network-on-Chips.
15 Virat Gandhi, 3D architectures.
16 L.Srivani, Synthetic Benchmark Circuits.
17 S.V.S. Suresh, Portable, Low Cost Five Lead Wireless ECG Device.
18 Sathya Narayanan, Proactive Channel Allocation MAC Protocols for Cognitive Radio Networks, 2016.