M.Tech - Degree Awarded

S.No Photo Thesis Title E-mail Id Current Position
1 T.B.N. Ambedkar, UDP Level Dynamic Power Estimation and Location of Power Hungry Nets, 2002. nrusimha@gmail.com ASE
2 John Prakash John, Circuit Partitioning Based Don't Care Identification, 2002. jpj_04@yahoo.com Lecturer
3 S. Krishna Kumar, Mapping of Logic Circuits To CPLD and LUT Based Hybrid FPGA Architecture, 2002. om_skkumar@yahoo.com Lecturer
4 Venugopal Naik, Logic Synthesis for FPGAs Using Embedded Memory Blocks, 2002. hello2venu@yahoo.co.in Software Engineer
5 Anjana K. R, A Synthesizable RTL model of an Instruction Decoder for the Intel x86 Core, 2004. anjanakr@hotmail.com
6 Bhargavi R, A Synthesizable RTL model of Context Infrastructure of the Intel x86 Core, 2004. bhargaviren@hotmail.com R & D Engineer
7 Shankar Umapathi, Automatic Assembly Program Generator for Hierarchical Descriptions of Processor Cores, 2004.
8 Chandramouli G, A Synthesizable RTL Model of the Decoder Unit of the Intel x86 Core, 2004. mouli_iit@yahoo.com
9 Murali Rajagopalan, A Synthesizable RTL model of the Control Unit of the Intel x86 Core, 2004.
10 Pradeepkumar S, A Synthesizable RTL model of an Arithmetic and Logic Unit of the Intel x86 Core, 2004.
11 V. K. Padhmanabhan, Functional Verification using Automatic Assembly Program Generator for Processors, 2004.
12 Ravi Yelamarthy, A Synthesizable RTL Model of an Arithmetic Logic Unit (MMX, SSE INTEGER INSTRUCTIONS) of the Intel x86 Core, 2005. yelamarthy_ravi@yahoo.com
13 Rajkumar G, A Synthesizable RTL Model of Floating Point Arithmetic and Logic Unit of the Intel x86 Core, 2005.
14 Maruthi Rao K, Verification of Integer and MMX units of the Intel x86 Core, 2005. maruthi20@yahoo.com
15 Mahesh Kumar E S, A Synthesizable RTL Model of Control Unit of the Intel x86 Core, 2005.
16 Ratna Kumar A, A Synthesizable RTL Model of Context Infrastructure and SSE2 of ALU of the Intel x86 Functional Model, 2005. ratnakumar_a@yahoo.com Software Consultant @ S.W.I.F.T Inc
17 Tinto James, A Synthesizable RTL Model of an Instruction Decoder for the Intel x86 Core, 2005. tintojames@yahoo.co.in
18 Ramesh Balan, Design and Implementation of Random Bit Generators in Hardware, 2005. rbalan66@rediffmail.com
19 Rahul Mallik, Implementation of Cryptographic Algorithms in Hardware, 2005. mallikradhul@rediffmail.com
20 Vinay Saripalli, Agile Algorithm-on-Demand CO-Processor, 2005. s.vinay@yahoo.com Technical Analyst
21 Prashant Mangalagiri, Automatic Assembly Program Generator for Verification of Processor Cores, 2005.
22 V.Karthik Venkataraman, Test Pattern Generation for Branch Predictor of a Superscalar Microprocessor Architecture using Constraint Solvers, May 2006. vkarthik.ee@gmail.com Senior Design Engineer
23 K. Senthil Kumar, Test Pattern Generation for Translation Lookaside Buffer of a Superscalar Microprocessor Architecture using Constraint Solvers, May 2006.
24 Archana Rai, Test Pattern Generation for Superscalar Processor: Reservation Station, Execution Unit and the Integration , using Constraint solvers, May 2006. raiarchana_26@rediffmail.com Senior Design Engg, LSI Technologies India Pvt Ltd.
25 Debi Prasad Mohapatra, Test Pattern Generation for Superscalar Processor: Cache, Register file and CDB Units, Using Constraint Solvers, May 2006. hello_debi@yahoo.com Senior CPU Design & Verification Engg, ARM Embedded technology India Pvt Ltd.
26 Ramaprasad. K, Memory Management Unit for the x86, May 2006. itsramprasad@gmail.com Design Engineer
27 E. Ramulu, A Synthesizable RTL Model of FP ALU & Context Infrastructure of x86 Core, May 2006. ramu_enugurthi@yahoo.com
28 B.Praveen, A Synthesizable RTL Model of SSE,SSE2 and SSE3 ALU's for INTEL x86 Core, May 2006. praveenb.mails@gmail.com
29 NVV Satya Suresh Chowta, Automatic Spatial Partitioning In Reconfigurable Environments, May 2006. suresh_chowta@yahoo.com Software Engineer
30 S. Nippan Kumar Reddy, Synthesis and Verification of INTEL x86 Core, May 2006. singamnipun@gmail.com
31 M. Pradeep, A Synthesizable RTL Model of Control Unit for the INTEL x86 Core, May 2006. pradeep134@gmail.com
32 P. N. Naveen Kumar, A Synthesizable RTL Model of Exception Unit for the INTEL x86 Core, May 2006. pn_naveen38@yahoo.com
33 K.Bala Raju, A Synthesizable RTL Model of Exception Handling for x86, May 2006. balarjuk507@yahoo.co.in Member Technical Staff
34 Pradeep Kumar, Development of Reconfigurable Agile Co-processor, May 2006.
35 Wg Cdr G Ananth, Kernel Development for a FPGA Based Reconfigurable Agile Co-processor, May 2006. anan_gv70@yahoo.com Wing Commander
36 US.Karthikeyan, Design of Programmable Interconnect Fabric for Multi FPGA Architecture, May 2006. us_karthi@yahoo.com
37 Poonam Gawade, Digitized True Random Number Generator using Ring Oscillators in FPGA, June 200 poonam_162@yahoo.co.in Senior Software Engineer
38 Aditya Raturi, An Agile Co-Procesor, June 2007
39 Chandra Sekhar Yapara, Control Transfer Instruction Design and Validation on the India Processor, May 2007 chandrasekhar_yapara@yahoo.com
40 Vidyavati S Nayak, Packet Processing Algorithms for Hardware Implementations,May 2007.
41 Praveen Kumar D, Design of a Generic Test Bed and Verification of Sequencer,June 2007. praveen_d_21@yahoo.com
42 Ashish Netam, Creation of Automatic Verification Environment, June 2007 ashishnetam@gmail.com Software Engineer
43 Venkatachalam Janarthanan, Performance Analysis of Sequential Workloads on LVM managed filesystems in EVMS environment, June 2007
44 Valliappan Ramasamy, Enterprise Volume Management System for RAID 5.0 Array, June 2007 vramasamy@inautix.co.in
45 Rajesh Thangamani, Understanding Enterprise Volume Management System in Linux and Performance Analysis of Sequential Workloads for a RAID 1.0 Array, June 2007
46 Mohammaed Shoaib, Concepts in Reliable and Optimal Systems Design,May 2008. shoaib.maks@gmail.com
47 Virendra Kumar Patidar, Sequential Test Power Reduction using Integrated Scan Cell and Test Vector Reordering Techniques, May 2008. virendrakumarpatidar@gmail.com
48 V. V. Narayana Rao, Double Tree Scan (DTS) Architecture for Shift Power Reduction in Scan Testing, May 2008. venkatnarayana.rao@gmail.com IBM
49 Dinesh Moparthi, A Simulation Study of Energy Efficient MAC Protocol in Wireless Sensor Network, May 2008. dinesh.m123@gmail.com
50 Santhosh Kumar K S, A Simulation Study of Energy Efficient Protocol in Wireless Sensor Network, May 2008. santhosh.sabawat@gmail.com
51 Umashankar Balasubramaniam, Wireless Sensor Network Solution for Data Center Environment Monitoring, May 2008.
52 Sumit Samajpati, Creation of Automatic Verification Environment, May 2008. sumit.samajpati@gmail.com Senior Software Engineer
53 Vankudothu Basha, Hardware Implementation for Pattern Matching, May 2008. bashanaik@gmail.com
54 Veerendra Kumar Niddapu, Implementation and Evaluating the Performance of Snapshot Techniques, May 2008. viru_myindia@yahoo.com
55 Chaudhari Parag Bhaskar, Modeling and Simulation of ATM Traffic Congestion Control, May 2008. paragbchaudhari@gmail.com
56 Soumya Dev Poriya, Design and Implementation of a Pattern Matching Hardware based on Artificial Neural Network, May 2008. soumyadev.poriya@gmail.com HSBC
57 Satya Gautham Merla, A System Level Simulation Environment for Hardware Transactional Memory, May 2008. merlagautham@gmail.com Project Manager
58 Akanksha Jain, Behavioural Test Pattern Development, May 2009. akansha.jain.87@gmail.com
59 Hrishikesh J, Power of Abstraction in Digital Design, May 2009. hrishi113@gmail.com PhD
60 Pranav Kumar, Formal Equivalence Checking of VME Bus Controller Design, May 2009. pranavkunwar@gmail.com Digital Design Engineer
61 Dhruv Ashok Rastogi, Parallel Approach to Fault Independent Combinational Redundancy Identification using CUDA, May 2009. dhruvrastogi@gmail.com Associate
62 Kommisetty Muralidhar, VLSI Implementation of Motion Vector Recovery Algorithms for H.264 Based Video Codecs, May 2009. kommisetty.muralidhar@gmail.com
63 K. Vivek Joy, Towards Acceleration of Logic Minimization using Graphics Processing Units, May 2009. vivekkjoy@gmail.com
64 P. Rathna Kumar, Towards Acceleration of Redundancy Identification using Graphics Processing Units, May 2009. rathnakr@gmail.com
65 J. Santhosh Kumar, Resurrecting Operating System, June 2009. santhu.j@gmail.com
66 P. Visweswara Rao, Efficiency Issues in Compilation of High-level Abstract Circuit Model, June 2009. vissu.pagoti@gmail.com
67 Balvir Kumar, Handling Cache faults by Dynamic Binary rewriting, May2010. kkbalvir@gmail.com Scientist 'D'
68 Deepak Tomar, Area and Power Analysis of Transactional Access Table based Hardware Transactional Memory, June 2010. tomdee16@gmail.com
69 Pradeep Jasti, Design Verification of Digital Circuits using High-level HDL, April 2010. kavuri.pradeep@gmail.com Associate System Engineer
70 Suchith Rajagopal, Air-borne Radar clutter simulation and signal processing using graphics processing unit, April 2010. suchithr@gmail.com
71 Gaurav Kumar Jain, Integer arithmetic and logic unit of ANUPAMA in Bluespec, May 2010. gaurav.eeiitm@gmail.com
72 Suresh Pakkala, Design of a Floating point unit for a 32-bit RISC processor - ANUPAMA, May 2010. suresh.30106@gmail.com
73 Aklesh Jain, Similarity based error concealment method for block-based coded images, May 2010. aklesh.iitm@gmail.com
74 Hema Venkata Krishna Giri Narra, Generating Synthetic Benchmark Circuits for Stress Testing FPGAS usin Particle Swarm Optimization, 2011.
75 Shankar Ganesh Ramasubramanian, Using Genetic Algorithm to generate Synthetic Benchmark Circuits to stress test FPGAs, 2011.
76 John C.James, Performance Enhancement of SONAR Data Processing using CUDA Framework, 2011. johnchuranadujames@gmail.com Scientist
77 K. Sathish Kumar, Performance Enhancement of Processes related to SONAR Data using CUDA Framework, 2011.
78 Abhinav Narain, Processing Large Scale Data for Prediction using Cloud Technology, 2011. abhinavnarain10@gmail.com
79 Mahesh Kopp, Parallel Processing System for Synthetic Aperture Radar Image Formation using GPU, 2011. mbkoppa@gmail.com
80 Satya Rama Kumar Pasumarthi Venkata Prasanna, Thermal-Safe Dynamic Test Scheduling Method Using OnChip Temperature Sensors for 3D MPSoCs, 2012.
81 Balaji Kommuru, Design and Development of Instruction Set Simulator for 32-bit RISC Processor Architecture, 2012. balaji.kommuru@gmail.com
82 Karthick S, Medium PRF Set Selection using PSO algorithm and its Parallelization for Airbone Pulse Doppler Radar, 2012. sjkarthick@gmail.com
83 Jagannadh Kashyap Garimella, Enhancing the Signature Scheme for Transactional Memory Systems, 2012.
84 Saketha, Using Secure Communication Processor to realize secure Banking server, 2012. ramasaketha@gmail.com
85 Raghuvaran D, Medium PRF Set Selection for Airborne Pulsed Doppler Radar Using Genetic Algorithm, 2012. raghu.dee@gmail.com
86 Kalyan Kumar Suvvada, Embedded SOC Design, 2012. kalyankumar.suvvada@gmail.com
87 SaiPraneeth Muddana, Design Proposals to Secure Pos Terminals, 2012. saipraneeth1@gmail.com
88 Sama Abhinay, Implementing Secure Boot on a low-cost processor for deploying in Point of Sale Terminals, 2012. abhinaysama@gmail.com
89 Arun Pushkar, Anomaly Detection Based Decision Support System For Network Intrusion Detection (DSSFNID), May 2013. arunpushkar@gmail.com Indian Army
90 Khaja Rahamthulla S K, Security Enabled Instruction Set Architecture for India Processor, May 2013.
91 Debiprasanna Sahoo, Implementation of "Memory Management Unit and Cache Controller, May 2013. debiprasanna.sahoo@gmail.com Software Development Engineer, Amazon India
92 Dinesh Parmar, Vector-Scalar Extension Instructions Implementation, April 2013.
93 Mehta Vandit Sunilbhai, Hardening of Android, May 2013. vandit.mehta89@gmail.com Member of Technical Staff, VMWare
94 Jaya Prakash,Porting of Fiasco Microkernel to Power PC Architecture, May 2013.
95 Bhaskar Reddy, Implementation of "Cache Coherence in Multicore System", May 2013. bhasker01.chitti@gmail.com Scientist 'C', RC1/DRDO
96 Suresh Kumar Meesala, Implementation of Dual Issue and out of Order execution for RISC processor, May 2013. suresh.meesala@gmail.com ASIC Engineer, CISCO
97 Vikas Kumar S, Implementation of Execution Units of a 64-bit RISC Processor, May 2013 . iamvik90@gmail.com Engineer, QUALCOMM
98 Mantha Shanmukh Abhishek,Design and Implementation of NVM Express Controller, May 2013. shanmukh.abhishek@gmail.com IC Design Engineer, BROADCOM
99 Avinash Merugu, Design and Implementation of "NAND Flash Controller", May 2013. avin.andreavusmars@gmail.com Graduate Engineer, ARM
100 Animesh Ghosh, Open Source Secure Router, May 2013. ani123mesh@gmail.com Indian Navy
101 Archana, Security Analysis and Customization of Android Platforms and Development of a Secure Messaging System, May 2013. archanasekhar1989@gmail.com SOC, BARC Mumbai
102 Senthil Kumar, Design and Implementation of Quad Issue and Out of Order Execution for Multithreaded Superscalar RISC processor, May 2014. senthilkr45@gmail.com Freescale Semiconductors, Noida
103 K Krishna Chaitanya, Implementation of Branch Predictor and Instruction Prefetch for Multi-threaded Superscalar Processor, May 2014. krishnac08@gmail.com Analog Devices India, Bangalore
104 Sachin Ramrao Waghmare, Design and Implementation of Fetch Decode and Issue stages for a Quad thread SMT RISC-V based Superscalar Processor, May 2014. sachin.wgme@gmail.com RGKTU
105 Saginala Sarath Yadav, Design and Implementation of S-stage Scalar in-order Pipelined Processor, May 2014. sarath03.27@gmail.com Analog Devices India, Bangalore
106 Keerthi Kiran Pujar, Design and Implementation of Multi-Channel NVM Express Controller, May 2014.
107 B N Avinash Varma, High Level Synthesis Using Assignment Decision Diagrams, May 2014.
108 Maloth Naresh, Secured Electronic Mail Application Development for L4-Microkernel, May 2014.
109 Pavankumar Reddy Muddireddy, High Level Synthesis Using Assignment Decision Diagrams, May 2014.
110 Anshu Kumar, Cache Coherent System Interconnect for RapidIO, May 2014.
111 Milan Patnaik, Proactive Workload aware Temperature Management Framework for Chip Multi-processors, May 2014. milanpatn@gmail.com Senior Manager, Government of India
112 Sampengala Vamsi Krishna, Porting L4/Fiasco Microkernel onto ARM Based Boards, June 2013.
113 Kaushik Raghavan R, Building a Secure Execution Environment for Freescale i.MX 6 Processor, May 2014.
114 Hari Krishna Bethapudi, Hardening Linux Kernels Server Distribution, May 2014.
115 Akshay Patil, NAND Flash API for Lightstor Framework, May 2014.
116 Sukrat Gupta, Fault Tolerant Microarchitecture for an In-Order RISC-V Processor, May 2015. sukratgupta@gmail.com
117 Anand Sai Verma, Design and Implementation of PCI express to serail Rapid IO Bridge, May 2015. anandsaiverma@gmail.com Scientist, DRDO
118 Ashutosh Kumar, Design and Implementation of Rapid IO Transmitter Module in Chisel, May 2014.
119 Madugula Srinivas Santhosh Kumar, Design and Implementation of Generic Multi-channel Storage Controller, May 2015.
120 Nishanth P. P., High level Synthesis using Conditional Decision Diagrams, May 2015.
121 Sireesh N, Design and Implementation of Out-of-order superscalar Processor, May 2015.
122 Gaddam Bharath Kumar, Implementation of Hybrid Memory Cube Interface, May 2015.
123 Venkatesh Bajjuri, Implementation of C-class Microcontroller SoC, May 2015.
124 Siddhant Saraf, Design for Testability for PINPOINT and Development of Power-Grid Modelling Framework, May 2015.
125 Laxmeesha S, Design and Implementation of ONFi 4.0 compliant "Nand Flash Controller", May 2015.
126 Ammannaidu Gedela, Implementation of Tagged Instruction Set Support for I-class Processor, May 2015.
127 Sunnihith Srivatsav, Trust Zone Support to I class Processor, May 2015. sunnihith1808@gmail.com Graduate Engineer, ARM, Bangalore
128 Segu Suresh, Design of Multi Master Single Slave AXI4 Protocol for RISC-V Processor, May 2015. suresh0447@gmail.com Qualcomm, Chennai
129 Chirag Garg, Enable Trustzone for LMX6 Processor, May 2015. chiragdthinker@gmail.com Member Technical Staff, NetApp, Bangalore
130 Raj Thakkar, Design and Implementation of a Multi-core Interconnect Fabric, May 2015.
131 Harshit Kumar Singh, Crossbar Based Four Port Switch for RapidIO IP cores using Bluespec, May 2015.
132 Paramesh O, ART on Genode OS Framework : Bionic Libe Porting, May 2015.
133 Praveen Srinivas B, Linux Virtualization on Genode, May 2015. srinivasprv@gmail.com Software Developer, Times Internet, Noida
134 Sai Sathvik Yepuri, Fabric for 32 Core Server Processor, May 2015.
135 Rachit Kumar, RapidIO RDMA Manager, May 2015.
136 Kushagra Varshney, ache Coherent System Interconnect for RapidIO, May 2015.
137 Nirmal Sheet, mplementation of Distributed Reservation Stations, May 2015.
138 L Siva Kumar, Design and Implementation of PCI express 3.0 Controller, May 2015.
139 Pradeep Kumar Reddy K, Native Filesystem for Genode Operating System Framework: The Second Extended Filesystem, May 2015.
140 Sujay K. Deshpande, Implementation of Parameterized Wallace Tree Multiplier, July 2015
141 Nandu Raj P, Verification Framework for RISC V Processor, January 2016.
142 Sanjeev Palkar, Development of Open Channel SSD Subsystem for LightStor, May 2016.
143 Kolla Srikanth, Implementation of MD5 Algorithm Using Reversible Logic, May 2016.
144 Pavan Kumar Posa, Integrating VLAN, LLDP, Multicast in Layer 2 Switch, May 2016.
145 Supritha Rathode Jatoth, Integrating VLAN,SNMP AND NTP in a Secure Switch, May 2016.
146 Adapa JanardhanaSwamy, Implementation of Tilelink protocol for Single Core Processor, May 2016.
147 K VenkataKrishna Rao, AXI Coherency Extensions, May 2016.
148 Chinnam Vishal Kumar,Ethernet Media Access Control Protocol(EMAC) Designing in Bluespec, May 2016.
149 Reena E, Implementing Cache Coherence through Manager-Client Pairing, June 2016.
150 Goutham Panneeru, Design and Implementation of Direct Memory Access Controller, May 2016.
151 Mohammed Unnisa Huluvallay, Issue Queue Optimisation of Out-of-Order Superscalar Processor, June 2016.
152 Bharati Mohan Dattaprasad, Advanced Debug Interface, June 2016.
153 D V H Phani Teja, 32-bit Graphics Processing Unit, June 2016.
154 Ramisetty Hari Prakash, Implementation of Advanced Debug Interface, June 2016.
155 Myneni Niteesh, Designing Fetch and Decode Units to Support Simultaneous Multithreading in a Superscalar Processor, June 2016.
156 Karilli Satish Kumar, Cache Coherence Implementation on Ring Bus, June 2016.
157 Sangmeshwar Mangrule, Vector Thread Processor, June 2016.
158 Raj Kamal, Five Stage Pipelined Processor for RISC-V compressed Instruction Set Architecture, June 2016.
159 Viraja Rama Gade, Implementation of Pipelined Router for Network on Chip (Mesh) submitted to IITM, May 2016.
160 Sivashyam Sundar A, Implementation of a Parameterized N-way Set Associative Banked L2 Cache, May 2016.
161 Ankit Bhatnagar, Quad Serial Peripheral Interface Design using Bluespec, June 2016.
162 Major Anirudh Agarwal, Soc Memory Controller using Bluespec System Verify, May 2017
163 Manish Kumar Maurya, 5 stage dual Issue Processor, May 2017
164 N. Sashidhar, Design and Implementation of DMA controller, May 2017
165 Debpratim Adar, Improving Performance of Quality Programmable Vector Processor using different Optimization, May 2017
166 Anjana A J, Design and Implementation of an Ordered Mesh network interconnect, May 2017
167 A Gaurav Sehgal, Ring based Architect for Distributed Shared Memory Chip Multiprocessor, May 2017
168 Rahul Singh Rajawat, A Non-Boolean Co-Processor Using Nano Oscillators, May 2017
169 Damarla Balaji, Design And Implementation of GPS L1 Signal Tracking And Data Processing For Position, May 2017
170 Syed M MD Zaid, Design And Implementation of GPS Receiver, May 2017
171 Shubham Chavan, Design and Implementation of DDR3 Memory Controller on Artix-7 FPGA, June 2017
172 P. Raghunandan, Two Level Cache Coherence Hierarchy, June 2017
173 Anvesh Babu, Advanced Debug Interface, June 2017