Publications in Referred National Conferences

  1. V. Kamakoti, "Dynamically Reconfigurable Fault-Tolerant Recursive VLSI Architecture", Proceedings of the First Fault-tolerant Computing Symposium, December 1995, IIT Madras.
  2. R. Chandrasekhar, V. Kamakoti, R. Rajaraman, N. Venketeswaran and C. R. Visvanath, "Dynamically Reconfigurable Fault-Tolerant VLSI Arrays", Proceedings of the Workshop on Real Time Embedded Computing Systems, Nov. 25-26, 1994, Association for Advancement of Fault-Tolerant and Autonomous Systems, Bangalore.
  3. Suchith Rajagopal and V. Kamakoti, Airborne Radar Clutter Simulation and Signal Processing using Graphics Processing Unit, International Radar Symposium, IEEE Bangalore Section, December 2011.
  4. Abhijit Pradhan, Sadhana Chevireddy, Kamakoti Veezhinathan and Hema Murthy, A low-bit rate segment vocoder using minimum residual energy criteria, In proceedings of the 16th National Conference on Communications Chennai, India, January 2010, pp. 246-250.

Publications in Referred International Conferences

    2017

  1. V. Gokulkrishnan, Seetal Potluri, Nitin Chandrachoodan and V. Kamakoti,A Scalable Pseudo-Exhaustive Search for FaultDiagnosis in Microfluidic Biochips, 30th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Cambridge, UK, Oct 2017.
  2. Arnab Ray, Swagath Venkatramani, Neel gala, Sanchari Sen, V. Kamakoti and Anand Raghunathan, A Programmable Event-Driven Architecture for Spiking Neural Network Evaluation, The International Symposium on Low Power Electronics and Design (ISLPED), Taiwan, July 2017.
  3. Arjun Menon, Subadhra Murugan, Chester Reberio, Neel Gala and V. Kamakoti, SHAKTI-T: A RISC V Processor with Light Weight Security Extensions, Workshop on Hardware and Architectural Support for Security and Privacy (HASP 2017) held in conjunction with ISCA 2017, Toronto, Canada.
  4. Rahul Bodunna, Neel Gala and V. Kamakoti, I-Class - A Many-core processor based on RISC-V, RISC V International Conference, Apr 2-3, 2017, Chennai,India.
  5. Satya Rajesh Medidi, M. Manimaran, N. Anil, Ankit Kumar, D. Thirugnana Murthy, K. Madhusoodanan and V. Kamakoti, Design of SHAKTI Processor based Safety Systems for Nuclear Power Plant, RISC V International Conference, Apr 2-3, 2017, Chennai, India.
  6. Arnab Roy, Swagath Venkatramani, Sanchari Sen, Neel Gala, Anand Raghunathan,and V. Kamakoti, A Programmable Event-driven Architecture for Spiking Neural Network Evaluation, Work-In-Progress Session, 53 rd Design Automation Conference, Austin, Texas, USA, June 18-22, 2017.
  7. 2016

  8. Neel Gala, Swagath Venkatramani, Anand Raghunathan and V. Kamakoti,STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection, International Symposium on Low Power E;electronics and Design (ISLPED), San Francisco, California, USA, August 8-10, 2016.
  9. Neel Gala, Swagath Venkatramani, Anand Raghunathan and V. Kamakoti, STOCK: Stochastic Checkers for Faults in Approximate Applications, Work-In-Progress Session, 52 nd Design Automation Conference, San Francisco, California, USA, June 7-11, 2016.
  10. Seetal Potluri, Satya Trinadh A, Siddhant Saraf and V. Kamakoti, Component Fault Localization using Switching Current Measurements, 21 st IEEE European Test Symposium, Amsterdam, Netherlands, May 24-27, 2016.
  11. Vikas Chauhan, Neel Gala and V. Kamakoti,ChADD: An ADD based Chisel Compiler with reduced Syntactic Variance, In Proceedings of 29 th International Conference on VLSI Design, Kolkata, January 6-8, 2016.
  12. 2015

  13. Seetal Potluri, A. Satya Trinadh, Siddhant Saraf and V. Kamakoti, Component fault localization using built-in current sensors for error resilient computation, First International ESWEEK Workshop on Resiliency in Embedded Electronic Systems, Amsterdam, The Netherlands, Oct. 2015.
  14. Sukrat Gupta, Neel Gala, G. S. Madhusudan Desikan and V. Kamakoti, SHAKTI-F: A Fault Tolerant Microprocessor Architecture, Asian Test Symposium (ATS 2015), Mumbai, Nov. 2015.
  15. Pavan Vithal Torvi, V. R. Devanathan, Aashish Vanjari and V. Kamakoti, SER mitigation techniques through selective flip flop replacement, To appear in 6th Asia Symposium on Quality Electronic Design, August 4-5, 2015, Kuala Lumpur, Malaysia.
  16. Patanjali SLPSK, Seetal Potluri and V. Kamakoti, HALTimer: a fast Vt replacement Heuristic for leakage power minimization using Adaptive Lazy Timer, Work-In-Progress Session, 52nd Design Automation Conference, San Francisco, California, USA, June 7-11, 2015.
  17. Satya Trinadh A, Sobhan Babu Ch., Shiv Govind Singh, Seetal Potluri and Kamakoti V, DP-fill: A Dynamic Programming approach to X-filling for minimizing peak test power in scan tests, To appear in Proceedings of 18th Design and Test in Europe (DATE) Conference, 2015, Grenoble, France.
  18. Seetal Potluri, Satya Trinadh Adireddy, S.G. Singh, Sobhan Babu Ch and Kamakoti V, Impact of Multi-Vt technique in Eliminating Thermal Runaway during Testing of 3D chips, Accepted for presentation in 3D Integration Technology, Architecture, Design, Package, Automation, and Test conducted as part of 18th Design and Test in Europe (DATE) Conference, 2015, Grenoble, France.
  19. Pavan Vithal Torvi, V.R. Devanathan and V. Kamakoti, Framework for selective flip-flop replacement for soft error mitigation, In proceedings of 28th International Conference on VLSI Conference, Bengaluru, India, (2015).

  20. 2014

  21. Deepthi T M, M S Sariga, K S Venkataraghavan, U Saravanan and V. Kamakoti, Development and Benchmarking of New Wireless Sensors for Structural Health Monitoring, Seventh ISSS International conference on Smart Materials, Structures and Systems, IISc, Bangalore, July 8-11, 2014.
  22. Samir Otiv, Kaushik Garlipati, Milan Patnaik and V. Kamakoti, H-Pattern: A Hybrid Pattern Based Dynamic Branch Predictor with Performance Based Adaptation, 4th JILP Workshop on Computer Architecture Competitions, held in conjunction with the 41st International Symposium on Computer Architecture, Minneapolis, USA, June 2014. (The paper won the Third prize in 4KB and 32KB category among the top-10 accepted papers).
  23. Patanjali SLPSK, Seetal Potluri and V. Kamakoti, Efficient Vt- Assignment to Minimize Circuit Leakage Using adapative Lazy timing analysis, Work-In-Progress Session, 51st Design Automation Conference, Moscone Center, San Francisco, California, USA, June 1-5, 2014.
  24. Neel Gala, V.R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti: ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs, 27th International Conference on VLSI Design 2014, Mumbai, pp. 342-347.

  25. 2013

  26. Shankar Raman, V. Kamakoti, Balaji Venkat and Gaurav Raina, Using timers to switch-off TCAM banks in routers, Proceedings of IEEE International Conference on Advanced Networks and Telecommunication Systems (ANTS), Chennai 2013.
  27. Abhijit Pradhan, Aswin Shanmugam S, Anusha Prakash, Kamakoti Veezhinathan and Hema A Murthy, A Syllable Based Statistical Text to Speech System, Proceedings of the European Signal Processing Conference (EUSIPCO), Marrakech, Morocco, 2013.
  28. Neel Gala, V.R. Devanathan, V. Visvanathan and V. Kamakoti, Tunable Stochastic Computing using Layered Synthesis and Temperature Adaptive Voltage Scaling, Proceedings of the 5th IEEE Asia Symposium on Quality Electronic Design (ASQED), Malaysia, 2013.
  29. Seetal Potluri, Satya Trinadh, Roopashree Baskaran, Kamakoti Veezhinathan, Nitin Chandrachoodan, PinPoint: An Algorithm for Enhancing Diagnostic Resolution Using Capture-Cycle Power Information, Proceedings of the 18th European Test Symposium (ETS), LIRMM, FRANCE, 2013.

  30. 2012

  31. S.V.S. Sures, R. Krishna Kumar and V. Kamakoti, Portable low cost 3 Lead wireless wearable ECG device, World Congress on Medical Physics and Biomedical Engineering, IFMBE Proceedings 39, pp. 13311334, 2012.
  32. Ashok Gautham, Kunal Korgaonkar, Patanjali SLPSK, Shankar Balachandran and Kamakoti Veezhinathan, Implications of Shared Data Synchronization Techniques on Multi-Core Energy Efficiency, Appeared in Proceeding of Workshop on Power-Aware Computing and Systems (HotPower-2012) held in conjunction with 10th USENIX Symposium on Operating Systems Design and Implementation (OSDI 12), October 2012, CS, USA.
  33. Kunal Korgaonkar, Kashyap Garimella and V. Kamakoti, Size-Proportional Signature Sharing for Transactional Memory Systems, Appeared in Proceedings of Future Architectural Support for Parallel Programming (FASPP'12), to be held in conjuntion with the 39th International Symposium on Computer Architecture (ISCA), June 2012.

  34. 2011

  35. S. Srinivasan, V. Kamakoti and A. Bhattacharya, Towards Improved Solutions for Generalized Placement Problem, International Symposium on Electronic Design (ISED), Kochin, December 2011.
  36. Kunal Korgaonkar, Prabhat Jain, Deepak Tomar, Kashyap Garimella and V. Kamakoti, Reconstructing hardware transactional memory for workload optimized systems, 9th International Conference on Advanced Parallel Processing Technologies, Lecture Notes in Computer Science, 2011, Vol. 6965, pp.1-15.
  37. Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini and Giovanni De Micheli, A Simulation Based Buffer Sizing Algorithm for Network on Chips, IEEE Annual Symposium on VLSI Design, July 2011, Chennai, pp.206-211.
  38. Seetal Potluri, Nitin Chandrachoodan and V. Kamakoti, Post-Synthesis Circuit Techniques for Runtime Leakage Reduction, IEEE Annual Symposium on VLSI Design, July 2011, Chennai, pp.319-320.
  39. M. Pawan Kumar, Anish S. Kumar, Srinivasan Murali, Luca Benini and V. Kamakoti, A Method for Integrating Network-on-Chip Topologies with 3D ICs, IEEE Annual Symposium on VLSI Design, July 2011, Chennai, pp.60-65.

  40. 2010

  41. R. Karthik Raghavan and V. Kamakoti, ROSY: A Fully-Software Solution to Recover from Hard Errors, Accepted as a Student Poster in the Fifteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2010), Pittsburgh, USA, March 2010.
  42. Kavish Seth, V. Kamakoti, S. Srinivasan, Fast motion vector recovery algorithm in H.264 video streams, SPIE proceedings of Multimedia on Mobile Devices, January 2010, DOI: 10.1117/12.843973.
  43. Lavanya Jagan, Camelia Hora, Bram Kruseman, Stefan Eichenberger, Ananta K. Majhi, V. Kamakoti, Impact of Temperature on Test Quality, 23rd International Conference on VLSI Design, Bangalore, India, pp.276-281, January 2010

  44. 2009

  45. Lavanya Jagan, Ratan Deep Singh, V. Kamakoti and Ananth Majhi, Efficient Grouping of Fail Chips for Volume Yield Diagnostics, In Proc. 22nd International Conference on VLSI Design, Bangalore, India, pp. 97-102, January 2009.
  46. Vasanth Ramesh, Akanksha Jain, V. Kamakoti and Vivekananda Vedula, Prime Numbers are High Coverage Test Vectors!, In Proc. of 13th IEEE Intl. VLSI Design and Test Symposium (VDAT'09), pp. 398-409.
  47. L. Srivani, V. Kamakoti and S. Ilango Sambasivan, Constructing Synthetic Benchmark Circuits to Stress Test FPGAs, In Proc. of 13th IEEE Intl. VLSI Design and Test Symposium (VDAT'09), pp. 135-145.
  48. K. Shyamala, M. Shoaib and V. Kamakoti, Peak Dynamic Power Estimation of FPGA-mapped Digital Designs, In Proc. of 13th IEEE Intl. VLSI Design and Test Symposium (VDA'09), pp. 155-166.
  49. Kavish Seth, Muralidhar Kommisetty, Vamshi Anand, V. Kamakoti and S. Srinivasan, VLSI Implementation of Motion Vector Recovery Algorithms for H.264 Based Video Codecs, In Proc. of 13th IEEE Intl. VLSI Design and Test Symposium (VDAT'09), pp. 336-346.
  50. N. Ramasubramanian, P. Krishnan, and V. Kamakoti, Studies on the Performance of Two New Bus Arbitration Schemes for MultiCore Processors, IEEE International Advance Computing Conference (IACC), 2009, pp. 1192-1196.

  51. 2008

  52. Karthik. K. S, Shyam. S, Ramasubramanian. N, Shoaib. M, Noor. M and Kamakoti. V., "A SEU Tolerant CLB RAM for In-Circuit Reconfiguration," Proc. of the 12th IEEE Intl. VLSI Design and Test Symposium (VDAT'08), pp.228-238, Jul 2008, Bangalore, India.

  53. 2007

  54. V. R. Devanathan, C.P. Ravikumar, and V. Kamakoti, A Stochastic Pattern Generation and Optimization Framework for Variation-Tolerant, Power-Safe Scan Test, Proceedings of the International Test Conference, October 2007, Santa Clara, USA, paper 13.1
  55. V. R. Devanathan, C.P. Ravikumar, and V. Kamakoti, PMScan : A Power-Managed Scan for Simultaneous Reduction of Dynamic and Leakage Power During Scan Test Proceedings of the International Test Conference, October 2007, Santa Clara, USA, paper 13.2.
  56. K. Najeeb, Vishnu Vardhan reddy, Siva Kumar Sastry Hari, V. Kamakoti and Vivekananda Vedula, "Power Virus generation using behavioral models," Proceedings of the VLSI Test Symposium (VTS) 2007, Berkeley, California, USA, pp. 35-42.
  57. V. R. Devanathan, C. P. Ravikumar and V. Kamakoti, "Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test," Proceedings of the VLSI Test Symposium (VTS) 2007, Berkeley, California, USA, pp.167-172.
  58. V. R. Devanathan, C. P. Ravikumar and V. Kamakoti, "On Power-Profiling and Pattern Generation for Power-Safe Scan Tests," Proceedings of IEEE Design Automation and Test in Europe (DATE), 2007, Nice, France, pp. 1-6.
  59. K. Vinay, Ratan Singh, S. Maleka, V. Kamakoti and Anirban Rahut, Delay Clock Methodologies for Timing-performance improvements of designs on FP-GAs, Proceedings of the 11th IEEE VLSI Design and Test Symposium, August 8-11, Kolkata, India, 2007
  60. K. Najeeb, Karthik Gururaj, V. Kamakoti and Vivekananda M. Vedula, "Controllability Driven Power Virus Generation for Digital Circuits," Appeared in the proceedings of the International Conference on VLSI Design, 2007, Bangalore, India, pp. 407-412
  61. V. R. Devanathan, C. P. Ravikumar and V. Kamakoti, "Reducing SoC Test Time and Test Power in Hierarchical Scan Test: Scan Architecture and Algorithms," Appeared in the proceedings of the International Conference on VLSI Design, 2007, Bangalore, India, pp. 351-356.
  62. Shoaib Mohammad, Noor Mohammad and V. Kamakoti, "A Genetic Approach to Gateless Custom VLSI Design Flow", Accepted for presentation in the 19th IEEE International Conference on Microelectronics, Cairo, Egypt, December 2007.
  63. Sanjay Burman, D. Mukhopadhyay and V. Kamakoti, "LFSR based Stream Ciphers are Vulnerable to Power Attacks," Appeared in Proceedings of the INDOCRYPT, Lecture Notes in Computer Science (LNCS 4859), Chennai, India, December 2007, pp. 384-392.

    2006

  64. K. Najeeb, P. Vishal Gupta, V. Kamakoti and V. Madhu Mutyam, "Delay and Peak Power Minimization for On-Chip Buses using Temporal Redundancy", Proceedings of the 16th ACM SIGDA Great Lakes Symposium on VLSI Design, Philadelphia, USA, pp. 119-122, April 2006.
  65. Kavish Seth, K. N. Viswajith, S. Srinivasan and V. Kamakoti, "Ultra Folded High-Speed Architectures for Reed-Solomon Decoders", Proceedings of the 19th IEEE/ACM-SIGDA International Conference on VLSI Design, January 2006, Hyderabad, India, pp. 517-520.
  66. Vivek Garg, Vikram Chandrasekhar, M. Sashikanth and V. Kamakoti, "An Area and Configuration-bit optimized CLB Architecture and Timing-Driven Packing for FPGAs", To appear in the proceedings of IEEE/ACM SIGDA International Conference on VLSI Design, 2006, Hyderabad, India, pp. 507-510
  67. H. Siva Kumar Sastry, Shyam Shroff, S. K. Noor Mahammad and V. Kamakoti, "Efficient Building Blocks for Reversible Sequential Circuit", Appeared in the Proceedings of the 49th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2006), Puerto Rico, August 2006.
  68. S. K. Noor Mahammad, H. Siva Kumar Sastry, Shyam Shroff and V. Kamakoti, "Constructing Online Testable Circuits using Reversible Logic", Appeared in the Proceedings of the 10th IEEE VLSI Design and Test Symposium (VDAT), Goa, India, August 2006, pp. 373-383.
  69. Debi Prasad, Archana Rai, Karthik Venkatraman, Senthil Kumar, V Kamakoti, Kailasnath S Maneperambil and Vivekananda M Vedula, "A Novel Unified Framework for Functional Verification of Processors using Constraint Solvers", Appeared in the Proceedings of the 10th IEEE VLSI Design and Test Symposium (VDAT), Goa, India, August 2006.
  70. V. R. Devanathan, C. P. Ravikumar and V. Kamakoti, "On Reducing Transition Fault Test Time and Test Power for SOCs in Hierarchical Scan Test," Proceedings of the First International IEEE Design and Test workshop, Dubai, Nov. 2006.

  71. 2005

  72. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, "Detecting SEU-caused Routing Errors in SRAM-based FPGAs", Eighteenth International Conference on VLSI Design, January 2005, Kolkata, India, pp. 736-741.
  73. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, "Cluster-based Detection of SEU-caused Errors in LUTs of SRAM-based FPGAs", Appeared in proceedings of the ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), January 2005, Shanghai, China, pp. 1200-1203.
  74. E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, "Efficient Methodology for Detection and Correction of SEU-based Interconnect Errors in FPGAs using Partial Reconfiguration (Extended Abstract)", Appeared in proceedings of the 13th ACM International Symposium on Field Programmable Gate Arrays, February 2005, Monterey, California, USA, pp. 265.
  75. E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, "Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-based FPGAs", Appeared in proceedings of the 12th Reconfigurable Architectures Workshop (RAW 2005), Colorado, USA.
  76. E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, "A CLB architecture for Online correction of SEU based Errors in LUTs of SRAM-based FPGAs", Appeared in the proceedings of the 10th European Test Symposium, (2005), Tallin.
  77. E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, "Efficient Methodology for Detection and Correction of SEU-based Interconnect Errors in FPGAs using Partial Reconfiguration", Appeared in the proceedings of the 10th European Test Symposium, (2005), Tallin.
  78. Noor Mohammad, Vikram Chandrasekhar, V. Muralidharan and V. Kamakoti, "Reduced Triple Modular Redundancy for Tolerating SEUs in SRAM-based FPGAs", Appeared in the proceedings of NASA International Conference on Military Applications in Programmable Logic Devices (MAPLD), September 2005, USA.
  79. CH. Sivasai Prasanna, N. Sudha, V. Kamakoti, "A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation", Appeared in the Proceedings of 18th International Conference on VLSI Design, January 2005, Kolkata, India, pp. 795-798.
  80. R.Pradeep, S.Vinay, Sanjay Burman and V. Kamakoti, "FPGA based agile algorithm-on-demand coprocessor", Appeared in proceedings of Design Automation and Test in Europe (DATE 2005), March 2005, Munich, Germany, pp. 82-83.
  81. R. Manimegalai, E. SivaSoumya, V. Muralidharan, B. Ravindran , D. Bhatia and V. Kamakoti , "Placement and Routing for 3D-FPGAs using Reinforcement Learning and Support Vector Machines", Appeared in the Proceedings of 18th International Conference on VLSI Design, January 2005, Kolkata, India, pp. 451-456.
  82. Vivek Garg, Vikram Chandrasekhar, Sasikanth and V. Kamakoti, "A Function Generator-based Reconfigurable System", Appeared in the proceedings of the IEEE/ACM SIGDA Asia South Pacific Design Automation Conference 2005 (ASPDAC), January 2005, Shanghai, China, pp. 905-909.
  83. Vivek Garg, Vikram Chandrasekhar, Sasikanth and V. Kamakoti, "A Novel Packing Algorithm for CLB Area Reduction", Appeared in the proceedings of the IEEE/ACM SIGDA Asia South Pacific Design Automation Conference 2005 (ASPDAC), January 2005, Shanghai, China, pp. 791-794.
  84. K. Uday Bhaskar, M. Prasanth, G. Chandramouli and V. Kamakoti, "A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip", Appeared in the Proceedings of 18th International Conference on VLSI Design, January 2005, Kolkata, India, pp. 207-212.
  85. K. Uday Bhaskar, M. Prashanth, V. Kamakoti and M. Kailasnath, "A Framework for Automatic Assembly Program Generator (A2PG) for Functional Verification and Testing of Processor Cores", Appeared in the proceedings of the Asia Test Symposium (ATS), December 2005, Kolkata, India.

  86. 2004

  87. Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, Balakuteswar V. Voleti, "A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation", 17th International Conference on VLSI Design, Mumbai, January 5-9, 2004, pp. 1071-1076.
  88. CH. Sivasai Prasanna, N. Sudha and V. Kamakoti, "A Hardware-directed Face Recognition system based on Local Eigen Analysis with PCNN", Appeared in the proceedings of International Conference on Neuro Information Processing (ICONIP), November 2004, Kolkata, India, pp. 327-332.
  89. A. Pavan Kumar, Sukhendu Das and V. Kamakoti, "Face Recognition Using Weighted Modular Principle Component Analysis", Appeared in the proceedings of International Conference on Neuro-Information Processing (ICONIP), November 2004, Kolkata, India, pp. 362-367
  90. A. Pavan Kumar, V. Kamakoti and Sukhendu Das, "An Architecture for Real Time Face Recognition using WMPCA", Appeared in the proceedings of Indian Conference on Computer Vision, Graphics and Image Processing (ICVGIP), December 2004, Kolkata, India, pp. 644-649.
  91. P. Pratibha, Siva Nageswara Rao Borra, A. Muthukaruppan, S. Suresh, and V. Kamakoti, "ASPIRE: Automatic Spatial Partitioning in Reconfigurable Environments Using Genetic Algorithms", Mexican International Conference on Artificial Intelligence, Lecture Notes in Computer Science (LNCS 2972), Mexico City, April 2004, pp. 735-745.
  92. P. Subrahmanya, R. Manimegalai, V. Madhu Muthyam, V. Kamakoti, "A Bus Encoding Technique for Power and Crosstalk minimization", 17th International Conference on VLSI Design, Mumbai, January 5-9, 2004, pp. 443-448.
  93. E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, "A Novel CLB Architecture to Detect and Correct SEU in LUTs of SRAM-based FPGAs", Appeared in the Proceedings of IEEE International Conference on Field-Programmable Technology (FPT), December 2004, Brisbane, Australia, pp. 121-128.
  94. A. Manoj Kumar, Jayaram Bobba and V. Kamakoti, "MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis", International Conference on Design Automation and Test in Europe, DATE 2004, Paris, France, February 2004, pp. 922-929.
  95. A. Manoj Kumar, Jayaram Bobba and V. Kamakoti, "SHAPER: Synthesis for Hybrid FPGA Architectures containing PLA elements using Reconvergence Analysis - (Extended Abstract)", Twelfth ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2004), Monterey, California, February 2004, pp. 251.
  96. R. Manimegalai, B. Jayaram, A. Manojkumar and V. Kamakoti, "SHAPER:Synthesis for Hybrid FPGAs containing PLAs using Reconvergence Analysis" Appeared in the proceedings of IEEE Field Programmable Technology (FPT), December 2004, Brisbane, Australia.
  97. Manoj Kumar A, Jayaram Bobba, R. Manimegalai and V.Kamakoti, "MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Arrays", 11th Reconfigurable Architectures Workshop (RAW 2004), Santa Fe, New Mexico, USA, April 2004.
  98. K Uday Bhaskar, G Chandramouli and V Kamakoti, "Pariksa- Functional Verification Tool for x86 Architecture", Appeared in the Proceedings of Eighth VLSI Design & Test Workshop (VDAT), August 2004, Mysore, India, pp. 492-502.

  99. 2003

  100. P. Pratibha, Siva Nageswara Rao Borra, A. Muthukaruppan, S. Suresh, V. Kamakoti, "An Enhanced Evolutionary Approach To Spatial Partitioning For Reconfigurable Environments", 2003 IEEE Congress on Evolutionary Computation, December 8-12, 2003, Canberra, Australia.
  101. M. Madhu, V. Srinivasa Murthy and V. Kamakoti, "Dynamic Coding Technique For Low Power Data Bus", Proceedings of IEEE Computer Society Symposium on VLSI, (ISVLSI 2003), Tampa, Florida, USA, pp. 252-253.
  102. L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani and V. Kamakoti, "Online Testing of Interconnect Faults in SRAM Based Reconfigurable Systems", Eighth IEEE European Test Workshop, (ETW 2003), The Netherlands.
  103. L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti and S. Suresh, "Online location of Multiple Faults in LUT Based Reconfigurable Systems", International Conference on VLSI Design 2003, (VLSI 2003), Las Vegas, USA, June 23-26, 2003, pp. 224-232.
  104. L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid and V. Kamakoti, "Testable Clock Routing Architecture for Field Programmable Gate Arrays", Thirteenth International Conference on Field Programmable Logic and Applications 2003, (FPL 2003), Lisbon, Portugal, Sept. 1-3, 2003, Lecture Notes in Computer Science (LNCS) vol. 2778, pp. 1044-1047.
  105. L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani and V. Kamakoti, "A Novel Method for Online In-Place Detection and Location of Multiple Interconnect in SRAM Based FPGAs", The Twelfth Asian Test Symposium, November 17-19, 2003, Xi'an, China.
  106. Jayaram Bobba, A. Manoj Kumar and V. Kamakoti, "Parallel Partitioning Techniques for Logic Minimization using Redundancy Identification", International Conference on High Performance Computing 2003, (HiPC 2003), Hyderabad, India, Dec. 17-20, 2003, pp. 174-183.
  107. Siva Nageswara Rao Borra, S. Suresh, A. Muthukaruppan and V. Kamakoti, "A Parallel Genetic Approach to the Placement Problem for Field Programmable Gate Arrays", Tenth Reconfigurable Array Workshop, (RAW 2003), Nice, France, pp. 184.
  108. A. Muthukaruppan, S. Suresh and V. Kamakoti, "A Novel Parallel Three Phase Genetic Approach to Routing for Field Programmable Gate Arrays", Proceedings of IEEE Field Programmable Technology 2003, Lecture Notes in Computer Science (LNCS) Vol. 2778, Hong Kong, pp. 336-339.
  109. P. Pratibha, Siva Nageswara Rao Borra, A. Muthukaruppan, S. Suresh, V. Ganesh and V. Kamakoti, "A Parallel Evolutionary Approach to Spatial Partitioning in Reconfigurable Environments", Indian International Conference on Artificial Intelligence, Hyderabad, December 2003, pp. 938-951.

  110. 2002

  111. A. Muthukaruppan, S. Suresh, Siva Nageswara Rao Borra and V. Kamakoti, "A Novel Three Phase Genetic Approach to Routing for Field Programmable Gate Arrays", Proceedings of Simulated Evolution And Learning 2002, Singapore, pp. 870-875.
  112. A. Muthukaruppan, S. Suresh and V. Kamakoti, "A Novel Evolutionary Approach to Routing for Field Programmable Gate Arrays", Artificial and Computational Intelligence 2002, Tokyo, Japan.
  113. S. Suresh, A. Muthukaruppan and V. Kamakoti, "A Novel Approach to Temporal Partitioning and Synthesis, Using an Evolutionary Algorithm Guided by ANN, for Reconfigurable Architectures", Artificial and Computational Intelligence 2002, Tokyo, Japan.
  114. A.Muthukaruppan, S.Suresh and V. Kamakoti, "A Three Phase Approach to Routing for Field Programmable Gate Arrays", Proceedings of International Conference on Knowledge Based Computing Systems 2002 (KBCS'2002), Mumbai, India. pp. 139-148.
  115. A. Muthukaruppan, S. Suresh and V. Kamakoti, "A Novel Parallel Evolutionary Approach to Routing for Field Programmable Gate Arrays", Proceedings of International Symposium on Advanced Intelligent Systems 2002, Tsukuba, Japan.
  116. S. Suresh, A. Muthukaruppan and V. Kamakoti, "A Parallel Genetic Approach to Temporal Partitioning And Synthesis for Reconfigurable Architectures", Proceedings of International Conference on High Performance Computing Asia 2002, Bangalore, India.
  117. S. Suresh, A. Muthukaruppan, Siva Nageswara Rao Borra and V. Kamakoti, "An Artificial Neural Network Guided Parallel Genetic Approach to the Routing Problem for Field Programmable Gate Arrays", Proceedings of International Conference on Neural Information Processing 2002, Singapore, pp.2645-2650.
  118. S. Suresh, A. Muthukaruppan and V. Kamakoti, "A Parallel Genetic Approach, using Artificial Neural Networks, to Temporal Partitioning and Synthesis for Reconfigurable Architectures", Proceedings of International Conference on Soft Computing and Intelligent Systems 2002, Tsukuba, Japan
  119. 2001

  120. K. Srinathan, C. Pandu Rangan and V. Kamakoti, "Toward Optimal Player Weights in Secured Distributed Protocols", Proceedings of Second International Conference on Cryptology, Lecture Notes in Computer Science (LNCS No. 2247), Springer Verlag, pp.232-241, Chennai, India, 2001.

  121. 1999

  122. Vr. Annamalai, C. S. Krishnamoorthy and V. Kamakoti, "Mesh Generation on a Hypercomputing Environment", Presentation in Asia - Pacific Conference on Applied Mechanics, (APCOM '99), Singapore, December 1999.

  123. 1998

  124. T. Graf, V. Kamakoti, N. S. Janaki Latha and C. Pandu Rangan, "The Colored Sector Search Tree: A Dynamic Data Structure for Efficient High Dimensional Nearest-Foreign-Neighbor Queries", Proceedings of the Fourth Annual International Computing and Combinatorics Conference (COCOON '98), held in Taipei, Taiwan, August 12-14, 1998.

  125. T. Graf and V. Kamakoti, "Reducing Simple Polygons to Triangles - a proof for an Improved Conjecture", Proceedings of the International Colloqium on Automata, Languages and Programming (ICALP'98), Denmark, July 13-17, 1998, Lecture Notes in Computer Science (LNCS), Springer Verlag, Vol. 1443, pp. 130-139, Kim G. Larsen, Sven Skyum, Glynn Winskel (eds.)
  126. T. Graf and V. Kamakoti, "Optimal Algorithms for Computing Visible Foreign Neighbors among Colored Line Segments", Proceedings of the Sixth Scandinivian Workshop on Algorithmic Theory, (SWAT '98), Stockholm, Sweden, July 8-10, 1998, Lecture Notes in Computer Science, Springer Verlag, Vol.1432, pp. 59-70.

  127. 1997

  128. T. Graf, N. S. Janaki Latha, V. Kamakoti and C. Pandu Rangan, "Optimal Parallel Algorithm for the all Nearest Foreign Neighbors Problem", Proceedings of the International Conference on High Performance Computing (HiPC), Bangalore, India, Dec 1997, IEEE press, pp. 132-136.
  129. V. Kamakoti and N. Balakrishnan, "Efficient Algorithms for Prefix and General Prefix Computations on Distributed Shared Memory Systems with Applications", Proceedings of the International Conference on Parallel and Distributed Systems, Korea, Dec 1997, pp. 44-51, IEEE press.
  130. T. Graf, V. Kamakoti and N. Balakrishnan, "Efficient Algorithm for the Nearest Neighbors Problem on Distributed Shared Memory Systems", Proceedings of the International Conference on High Performance Computing Asia 1997, Seoul, Korea, April 1997, pp. 367-372, IEEE press.

  131. 1996

  132. V. Kamakoti and C. Pandu Rangan, "Efficient Algorithm for testing the Adder and General Boolean Circuits using Randomization", Proceedings of the Fourth International Conference on Advanced Computing, Bangalore, Dec. 1996, pp. 100-107.
  133. V. Kamakoti and N. Balakrishnan, "Efficient Algorithm for the Assignment Problem on Distributed Shared Memory Systems", Proceedings of the Fourth International Conference on Advanced Computing, Bangalore, Dec. 1996, pp. 44-51.

  134. 1995

  135. V. Kamakoti, Kamala Krithivasan and C. Pandu Rangan, "Efficient Randomized Incremental Algorithm for the Closest Pair Problem using Leafary Trees", First Annual International Computing and Combinatorics Conference (COCOON '95), Xi'an, China, August 24-26, 1995, Lecture Notes in Computer Science (LNCS) No. 959, Springer Verlag, pp. 71-80.

  136. 1994

  137. P. Jagan Mohan, V. Kamakoti and C. Pandu Rangan, "Efficient Randomized Parallel Algorithm for the Closest Pair Problem in D-Dimensions", Proceedings of the 13th World Computer Congress, Vol. 1. Hamburg, Germany, pp. 547 - 552, 1994.

  138. 1991

  139. V. Kamakoti et al, "A Special Purpose Silicon Compiler for Designing Super Computing VLSI Systems", Proceedings of the 3rd NASA Symposium on VLSI Design, Moscow, USA, pp. 13.1.1 - 13.1.15, 1991.