Design Verification using Specman

Instructions for interfacing Specman with Modelsim

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  1. Setting up the environment variables

  2. Check for the required files

  3. Generation of the stub file

  4. Compiling the stub file with the design

  5. Starting the simulation

  6. The Specman-Modelsim Interface

  7. For the quick and the impatient :-)

  8. Documentation



Setting up the environment variables

This is a demo that shows how to use specman and verilog simulators for design verification. Before we proceed further, let us create a folder called example1. This is done by typing "mkdir example1" at the command prompt.













There are six environment variables that need to be set before using the verification tools from RISE lab. These are:

A shell script that sets up these environment variables can be obtained here. Download this file into example1 folder and type “source setup_Specman.sh” command to setup the variables.




Check whether the environment variables have been properly set by typing "env" at the command prompt.


Alternately, you can update your .bashrc file with the contents of setup_Specman.sh. The .bashrc file is located in your home folder. If such a file does not exist, simply create one and update it.

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Check for required files

  1. Download the design file (design.v) from here into example1/ folder.

  2. Download the verification file (design.e) from here into example1/ folder.

  3. Download modelsim.ini file from here into example1/ folder.

Type "ls" at the prompt to check whether these files are present in the folder.



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Generation of the stub file

The following command shall generate a stub file called specman.v




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Compiling the stub file with design

The following set of commands compiles the stub file generated in the previous step and the design file.

vlib work” will create a working directory for Modelsim

vlog specman.v design.v” shall compile the stub file and the design file.



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Starting the simulation

The following sequence of commands will enable one to simulate a design in modelsim using stimuli generated by specman:

First, invoke the verilog simulator by typing “vsim -keepstdout -c topMod specman” at the prompt. Here, topMod is the top-level module of design.v and specman is the top-level module of specman.v .



Then invoke the specman simulator from VSIM prompt typing the command “sn” at the VSIM prompt.



This will take you to the specman prompt. There, type "load design" command to load the e file called design.e into the specman simulator:



After loading the e file, type "test" at the specman prompt to generate the stimuli:



To exit specman and return back to modelsim (VSIM prompt), just press the return key once. (You can get back to specman prompt by typing "sn" again at the VSIM prompt. This way, you can shuttle back and forth between specman and modelsim simulators.)



To run the simulation for, say 1000 time steps, type the following vsim command at the VSIM prompt:



After a successful simulation run, you should see a message like the one shown below:



Type “exit” at the VSIM prompt to exit the verilog simulator.



All the above steps can be done in one go by using this script at the command prompt.


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The Specman-Modelsim Interface




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For the quick and the impatient :-)

Download example1.tgz. This is a compressed file. Uncompress this file using the command "tar -xvzf example1.tgz". This would create a folder called example1. Navigate into this folder and source the setup_Specman.sh script using "source setup_Specman.sh" command. To run the simulation, type "./verify.sh" at the command prompt. Congratulations! You have successfully executed the demo!

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Documentation


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Design Verification using Specman and Modelsim
Last Updated on :March 11
, 2009
Web Page Created by Vasanth K Ramesh
IIT Madras, Chennai -
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