Publications in Referred National Journals

  1. V. Kamakoti and C. Pandu Rangan, "Efficient Transitive Reduction of Permutation Graphs and its Applications", Journal of Computer Science and Informatics Computer Society of India, Vol. 23, No. 3, pp. 52-59, 1993.
  2. N. Sudha, CH Siva Sai Prasanna and V. Kamakoti, "An Efficient Digital Architecture for Principal Component Neural Network and its FPGA Implementation", IETE Journal of Research, Vol. 53. No. 5, pp. 425-432, Sept-Oct 2007.
  3. Lavanya Jagan and V. Kamakoti, "Test and Diagnostic Trends for Nanometer Technology", IETE Technical Review. Vol. 27 (6), pp. 430-445, 2010.
  4. Kavish Seth, V. Kamakoti and S. Srinivasan, "Motion Vector Recovery based Error Concealment for H.264 Video Communication: A Review", IETE Technical Review, Vol. 28 (1), pp. 29-39, 2011.
  5. V. Kamakoti and Kunal Korgaonkar Kishore, "Thread Synchronization: From Mutual Exclusion to Transactional Memory", IETE Technical Review, Vol. 28 (4), pp. 302-315, 2011.
  6. Karthik Raghavan and V. Kamakoti, "Utilizing Faulty Cores", IETE Technical review, Vol. 28 (5), pp. 400-409, 2011.
  7. Pawan Kumar, Srinivasan Murali and V. Kamakoti, “3-D Network-on-Chips:Past, Present and Future”, IETE Technical review.
  8. L. Srivani and V. Kamakoti, “Synthetic Benchmark Circuits”, IETE Technical Review, Vol. 29 (6), pp. 442-448, 2012.
  9. S. Srinivasan, V. Kamakoti and A. Bhattacharya, “A Review of algorithms for Border Length Minimization Problem,” IETE Technical Review, Vol. 31(5), 2014, DOI: 10.1080/02564602.2014.959078.
  10. S. Srinivasan, V. Kamakoti and A. Bhattacharya, “Theoretical Lower Bound for Border Length Minimization Problem, Sankhya, pp 1-20, 2016, doi=”10.1007/s13571-016-0121-y”

Publications in Referred International Journals

  1. V. Kamakoti and C. Pandu Rangan, "An Optimal Algorithm for Reconstructing a Binary Tree", Information Processing Letters, Vol. 42, pp. 113-115, 1992.
  2. K. Arvind, V. Kamakoti and C. Pandu Rangan, "Efficient Parallel Algorithms for Permutation Graphs", Journal of Parallel and Distributed Computing, 26:116-124, 1995.
  3. V. Kamakoti, Kamala Krithivasan and C. Pandu Rangan, "Efficient Randomized Algorithms for the Closest Pair Problem on Colored Point Sets", Nordic Journal of Computing, 2:28-40, 1995.
  4. T. Graf and V. Kamakoti, "Sparse Dominance Queries for many points in Optimal time and Space", Information Processing Letters 64:287- 291, 1997.
  5. Vr. Annamalai, C.S. Krishnamoorthy and V. Kamakoti, "Adaptive Finite Element Analysis on a Parallel and Distributed Environment", Journal of Parallel Computing - Special Issue on High Performance Computing for Automotive Industries, pp. 1413-1434, 1999.
  6. V. Kamakoti and N. Balakrishnan, "Efficient Randomized Algorithms for the Closest Pair Problem on Distributed Shared Memory Systems", International Journal of Mathematical Algorithms, Vol. 1, No. 2, pp. 81-105, 1999 [ISSN 1027-9350].
  7. L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid and V. Kamakoti, "Pseudo-online testing methodologies for various components of field programmable gate arrays", Microprocessors and Microsystems, Vol.29, (2005) pp. 99-119.
  8. K. Najeeb, Vishal Gupta, V. Kamakoti and Madhu Mutyam, "Temporal Re-dundancy Based Encoding Technique for Power and Delay Reduction of On-Chip Buses," Journal of Low Power Electronics, Vol. 2, No. 3 (2006), pp. 425-436.
  9. V. R. Devanathan, C. P. Ravikumar and V. Kamakoti, “On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores,” Journal of Low Power Electronics, Vol. 2, No. 3 (2006), pp. 464-476.
  10. Siva Nageswara Rao Borra, Annamalai Muthukaruppan, S. Suresh and V. Kamakoti, “A Novel Approach to The Placement and Routing Problems for Field Programmable Gate Arrays”, International Journal on Applied Soft Computing, (7) 2007, pp. 455-470.
  11. A. Pavan Kumar, V. Kamakoti and Sukhendu Das, “System-on- Programmable-Chip for Face Recognition using WMPCA”, Pattern Recognition Letters, 28 (2007), pp. 342-349.
  12. V. R. Devanathan, C. P. Ravikumar and V. Kamakoti, “Variation-Tolerant, Power-Safe Pattern Generation and Optimization frame work”, IEEE Design and Test of Computers, vol 24, pp. 374-384, Jul - Aug 2007.
  13. K. Najeeb, Karthik Gururaj, V. Kamakoti and Vivekananda M. Vedula, "Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits," Journal of Low Power Electronics Vol. 3 No. 3, pp.280-292, 2007.
  14. Siva Kumar Sastry , Vishnu Vardhan Reddy, V. Kamakoti, V. M. Vedula and M. Kailasnath, "Automatic Constraint Based Test Generation for Behavioural HDL Models," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 4, pp. 408-421, April 2008.
  15. V. R. Devanathan, C. P. Ravikumar, Rajat Merhotra and V. Kamakoti, "A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction," Journal of Low Power Electronics Vol. 4, No. 1, pp.101-110, 2008.
  16. Sk Noor Mahammad, and V Kamakoti, Constructing Online Testable Circuits using Reversible Logic, IEEE Transactions on Instrumentation and Measurements.
  17. George Kurien, V. V. Narayana Rao, Virendra Patidhar, V. Kamakoti and Srivaths Ravi, An integrated SCR and TVR Technique for shift power reduction on Linear and Double-Tree Scan architectures, Journal of Low Power Electronics.
  18. Kunal K., George K., Satya Gautam and V. Kamakoti, HTM Design Spaces: Complete Decoupling From Caches and Achieving Highly Concurrent Transactions, ACM SIGOPS Operating Systems Review, Vol. 43 (2), 98-99, 2009.
  19. K. Shyamala, J. Vimalkumar, and V. Kamakoti , Novel SAT-Based Peak Dynamic Power Estimation for Digital Circuits , Journal of Low Power Electronics.5, 429438 December 2009.
  20. Kavish Seth, V. Kamakoti and S. Srinivasan, Efficient Motion Vector Recovery Algorithm for H.264 using Directional Interpolation, IET Journal of Image Processing, Vol. 4, Issue 2, April 2010, pp. 132-141.
  21. Kavish Seth, V. Kamakoti and S. Srinivasan, Efficient Motion Vector Recovery Algorithms for H.264 using B-Spline Approximation, IEEE Transactions on Broadcasting, Vol. 56 (4), 2010, pp. 467-480.
  22. Shoaib Mahammad, Noor Mahammad and V. Kamakoti, Hardware based Genetic Evolution of Self-Adaptive Arbitrary Response FIR Filters, Journal of Applied Soft Computing, Vol. 1 (11), 2011, pp. 842-854, Elsevier.
  23. Karthik Raghavan and V. Kamakoti, ROSY: recovering processor and memory systems from hard errors, ACM SIGOPS Operating Systems Review, Vol. 45, No. 3, 2011, pp. 82-94.
  24. Anish S Kumar, M Pawan Kumar, Srinivasan Murali, V Kamakoti, Luca Benini and Giovanni De Micheli, A Buffer Sizing Algorithm for Network on Chips with mutiple Voltage-Frequency Islands, Journal of Electrical and Computer Engineering, Hindawi Publications.
  25. S. Srinivasan and V. Kamakoti, A Novel Algorithm for Fast Synthesis of DNA Probes on Microarrays, ACM Journal of Emerging Technologies in Computing.
  26. Seetal Potluri, Nitin Chandrachoodan, and V. Kamakoti, Interconnect Aware Test Power Reduction, Journal of Low Power Electronics, Vol. 8, pp. 516-525, 2012.
  27. Rama Kumar Pasumarthi, V. R. Devanathan, V. Visvanathan, Seetal Potluri, and V. Kamakoti, Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs, Journal of Low Power Electronics, Vol. 8, 684-695 (2012).
  28. Virat Gandhi, V. R. Devanathan, V. Visvanathan, Milan Patnaik and V. Kamakoti, Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions, Journal of Low Power Electronics, Vol. 9, 207-220 (2013).
  29. A. Satya Trinadh, Seetal Potluri, Ch. Sohan Babu and V. Kamakoti, An Efficient Heuristic for Peak Capture Power Minimization During Scan-Based Test, Journal of Low Power Electronics, Vol. 9, 264-274 (2013).
  30. K. Shyamala and V. Kamakoti, ReMap: A Novel Automated Peephole Optimization Based Approach for Logic, Delay and Power Minimization, Journal of Low Power Electronics, Vol. 10, 20-31 (2014).
  31. A. Satya Trinadh, Seetal Potluri, Shankar Balachandran, Ch. Sobhan Babu, and V. Kamakoti, XStat: Statistical X-Filling Algorithm for Peak Capture Power Reduction in Scan Tests, Journal of Low Power Electronics, Vol. 10, 107-115 (2014).
  32. L. Srivani, N. H. V. Krishna Giri, Shankar Ganesh, V.Kamakoti, Generating Synthetic Benchmark Circuits for Accelerated Life Testing of Field Programmable Gate Arrays using Genetic Algorithm and Particle Swarm Optimization, Applied Soft Computing, Vol. 27, pp.179-190, (2015).
  33. Milan Patnaik, R. Chidambaranathan, Chirag Garg, Arnob Roy, V. R. Devanathan, Shankar Balachandran and V. Kamakoti, ProWATCh: A Proactive Cross-Layer Workload Aware Temperature Management Framework for Low-Power CMPs, ACM Journal on Emerging Trends in Computing, Vol. 12 (3), 2015.
  34. Neel Gala, V. R. Devanathan, V. Visvanathan, and V. Kamakoti, Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate ASICs Targeting Media-Based Applications, Journal of Low Power Electronics, Vol. 11, pp. 133-148, 2015.
  35. Seetal Potluri, A. Satya Trinadh, Sobhan Babu, V. Kamakoti, and Nitin Chandrachoodan, DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing, ACM Transactions on Design Automation of Electronic Systems, Vol. 21 (1), November 2015.
  36. Sanjay Burman, Seetal Potluri, Debdeep Mukhopadhyay and V. Kamakoti, Power Consumption Vs Hardware Security: Feasibility Study of Differential Power Attack on LFSR based stream ciphers and Its Countermeasures, Journal of Low Power Electronics, Vol 12, No. 2, pp. 91-98, June 2016.
  37. N. Satyanarayanan, Milan Patnaik and V. Kamakoti, ProMAC: A Proactive Model Predictive Control based MAC Protocol for Cognitive Radio Vehicular Networks, Computer and Communications, Elsevier, Special Issue on Multi-radio, Multi-technology, Multi-system Vehicular Communications, Vol. 93,Issue C, pp. 27-38, Nov. 2016.
  38. Neel Gala, Swagath Venkatramani, Anand Raghunathan and V. Kamakoti, Approximate Error Detection with Stochastic Checkers, IEEE Transactions on Very Large Scale Integration Systems, Vol. 25, Issue 8, pp. 2258-2270, Aug. 2017.
  39. Neel Gala, Saradha Krithivasan, Wei-Yu Tsai, Xueqing Li, Vijaykrishnan Narayanan, and V. Kamakoti, An Accuracy Tunable Non-Boolean Co-Processor using Coupled Nano-oscillators, To Appear in ACM Journal on Emerging Trends in Computing.
  40. Satya Trinadh, Seetal Potluri, Sobhan Babu, Shiv Govind Singh and V. Kamakoti, Optimal Don’t Care Filling for Minimizing Peak Toggles during At Speed Stuck-at Testing, To appear in ACM Transactions on Design Automation of Electronic Systems.