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Neel Gala

Project Officer @ RISE LAB



Email    : neelgala[at]gmail[dot]com

Contact : 0091 - 9962550582



Curriculum Vitae



About Me

I have completed my B-Tech from NIT-Warangal in Electronics and Communication Engineering in year 2010. In the last quarter of 2010, I joined IIT-Madras as a project associate for a period of 18 months working on the development of indigenous processors and micro-controllers for multiple Indian Defense organizations. In January 2012 I joined the Computer Science and Engineering Dept. at IIT-Madras as a Direct PhD Candidate with Prof. V. Kamakoti as my advisor.

My primary area of research during my PhD was in exploring alternate low-power computing paradigms such as Approximate computing, Stochastic Computing, Non-Boolean computing, etc. I have also been a recipient of the TCS Phd Scholarship for 2 consecutive years. I also hold a US Patent in collaboration to Texas Instruments Bangalore. After completing my PhD in 2016, I now works at RISE Lab as a Project Officer leading the SHAKTI Open source hardware initiative and also collaborating on research fronts with multiple researchers across the world in the domains of computer architecture, low power vlsi, memory consistency models, system security and neuromorphic computing.

Education

Indian Institute of Technology Madras    (2012 - 2016)

PhD in Computer Science and Engineering

National Institute of Technology Warangal    (2006-2010)

B.Tech in Electronics and Communications Engineering

Patents

Configuration aware, Tunable Stochastic Design Framework, without Voltage Scaling


United States Patent Applications


Click here for Abstract

Publications [16]

Vikas Chauhan, Neel Gala, G. Srinivasan, V. Kamakoti, “ChADD: HLS of Chisel Designs using ADDs”, communicated to ACM TODAES, April 2017

Arjun Menon, Subadra M., Cheter R., Neel Gala, V. Kamakoti, “Shakti-T : A RISC-V Processor with Light Weight Security Extensions”, communicated to Hardware and Architectural Support for Security and Privacy (HASP) 2017.3.

Arnab Roy, Swagath Venkataramani, Neel Gala, Anand Raghunathan, V. Kamakoti, “A Programmable Event-driven Architecture for EvaluatingSpiking Neural Networks”, communicated to International Symposium on Low Power Electronics and Design (ISLPED), 2017.

Neel Gala, Sarada Krithivasan, Wei-Yu Tsai, Xueqing Li, Vijaykrishnan N. V. Kamakoti, “An Accuracy Tunable Non-Boolean Co-processor using Coupled Nano-oscillators”, accepted in ACM Journal of Emerging Technologies in Computing (JETC), April, 2017.

Neel Gala, Swagath Venkatramani, Anand Raghunathan, V. Kamakoti, “Approximate Error Detection with Stochastic Checkers”, accepted in IEEE Transactions in VLSI (TVLSI), March, 2017.

Neel Gala, Arjun Menon, Rahul Bodduna, G. S. Madhusudan, V. Kamakoti, “SHAKTI Processors: An Open-Source Hardware Initiative”, IEEE International conference on VLSID, 2016.

Neel Gala, Swagath Venkatramani, Anand Raghunathan, V. Kamakoti, “STOCK: Stochastic Checkers for low-overhead error detection”,accepted, ISLPED, 2016.

Neel Gala, Swagath Venkatramani, Anand Raghunathan, V. Kamakoti, “STOCK: Stochastic Checkers for faults in Approximate Applications”, Work-in-Progress, DAC 2016.

Arnab Roy, Neel Gala, V. Kamakoti, Swagath Venkatramani, Anand Raghunathan, “Event-Driven Processing Architecture for Neuromorphic Computing”, poster at Workshop on Computational Brain Research, IIT-Madras, 2016

Swagath Venkataramani, Anand Raghunathan, Neel Gala, Sanjay Ganapathy, Balaraman Ravindran , V. Kamakoti, “Stochastic Computing : Information Processing with Bitstreams”, poster at Workshop on Computational Brain Research, IIT-Madras, 2016

Vikas Chauhan, Neel Gala and V. Kamakoti, “ChADD: An ADD based Chisel Compiler with reduced Syntactic Variance”, VLSI Design ,IEEE, 2016.

Sukrat Gupta, Neel Gala, G. S. Madhusudan and V. Kamakoti, “SHAKTI-F : A Fault Tolerant Microprocessor Architecture.”, Asian Test Symposium, IEEE, 2015.

Neel Gala, V. R. Devanathan, V. Visvanathan and V. Kamakoti “Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications ”, Journal of Low Power Electronics, June 2015

Neel Gala, V. R. Devanathan, K. Srinivasan, V. Visvanathan, and V. Kamakoti, “ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs”, in the Proceedings of the 27 th International Conference on VLSI Design, .pp 342-347, 2014.

Nihar Rathod, Shankar Balachandran, Neel Gala, “CAERUS: an effective arbitration and ejection policy for routing in an unidirectional torus”, in the Proceedings of the 8th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip, 2014

Neel Gala, V. R. Devanathan, V. Visvanathan, V. Gandhi and V. Kamakoti, ”Tunable stochastic computing using layered synthesis and temperature adaptive voltage scaling”, in the Proceedings of the 5 th Asian Symposium on Quality Electronic Design (ASQED),.pp 103-112, 2013.

Mini Projects

IITiMer

I have co-authored the IITiMer, which is a static timing analysis engine developed by the Indian Institute of Technology, Madras. Written completely in standard C. The performance (memory, runtime) and simplicity of the code makes IITiMer a convenient starting point for academic research. A multi- threaded and statistical (variation aware) variant of the IITiMer is available for use. The static version has APIs provided which enables better debugging of the result. The static version has been used as a Timer in the ICCAD 2014 Contest. Current work at IITM, focuses on parallelism of the code to further improve performance and memory requirements. The link to the repo is here

Library Characterization

Developed a library characterization tool as a part of the “CAD for VLSI“ course. The tool, developed in python, takes a standard library (Synopsys Liberty format) previously characterized at nominal conditions and outputs a new library which is now characterized at a new temperature and/or voltage and/or process strength. Only a subset of gates of the original library such as AND, OR, XOR, NOR etc. were chosen for this project. The characterization was done using ELDO tool from Mentor Graphics for a 65nm technology node from UMC. Challenge lied in characterizing flip-flops for such variations.

VLSI Tools

During the “VLSI Design Automation Algorithms“ course a number of small python based tools for placement, routing, boxing, packing etc. were developed. The challenge was to use coding techniques to handle large data sets and use libraries and available optimization tool-boxes.

Branch Predictor

This project was completed along with the “Computer Architecture“ course. I was tagged with another student and we developed a global branch-predictor which was integrated into a toy 5 stage pipelined processor. The entire development was done using Bluespec.

Low Power Router

This work involved creating a fully parameterized low-power on-chip interconnection router. The idea is a modified version of the famous Paternoster router. The challenge was to leverage the parameterizability offered by Bluespec in developing the design. This work and other scripts for various tools can be found at Bitbucket Repo

Experience

IIT-Madras

Project Officer

July 2016-Present

I am leading the team in the design, development, verification and synthesis of the SHAKTI Processors.

Texas Instruments India Ltd.

Intern

Feb-Aug 2013

During my internship, I was given a chance to work on various problems related to “Stochastic and Approximate Computing Designs“ under the mentorship of Dr. V. Devanathan. My initial work dealt with approximating an open-core H.264 video decoder such that we gain graceful degradation in quality with significant power savings. I then proceeded to work on a GPU class of applications and hardware. The details of the work can be found in the published papers. I also had a chance to work on some of TI’s imaging IP. The internship gave me huge exposure to the industry standards, tools and software.

RISE LAB.

Project Associate

Aug 2010 - Jan 2012

Worked on the development of a complete indigenous super-scalar 32-bit RISC micro-processor for the DRDO using Bluespec System Verilog. The the ISA was provided by DRDO, the micro-architecture on the other hand was design in-house at RISE LAB. My contribution was developing the complete code skeleton from scratch including MMU, reservation stations, execution units, etc. This processor is under verification stage.

Along side, a minimized version of the same processor (with lesser ISA support) was integrated with various peripherals such as SPI, I2C, etc to build a hardware secure SoC. This SoC is currently under prototyping phase.

RISE LAB

Summer Intern

May-Jun 2009

The project involved understanding the efficiency of a new HDL- Bluespec System Verilog (BSV) in equivalence checking. The DUT was a Stand Alone Finite Impulse Test (SAFIT) unit. Idea was to leverage the automated control logic solution of BSV and verify the quality of the design and its efficiency in terms of ease of design and ability to meet the final requirements. This excersize gave me exposure to some of the important industrial tools such as Formal-Pro, Modelsim, VCS etc.

Bhabha Atomic Research Centre

Summer Intern

May-July 2008

This project was undertaken at the end of my 2nd year of undergraduate studies at BARC. The work involved designing a Test-bench in VHDL for the verification of hardware circuits such as Scalar-Timer and Ramp Generator which were targeted for a Prototype Fast Breeder Reactor. The final test-bench was burned into the on-board Actel FPGA using Libero. The working of the entire system was then verified on a real-time digital oscilloscope by probing various inputs/outputs of the system. The project introduced me digital design, HDLs and hardware design.

Technical Skills

  • Bluespec
  • C/C++
  • bash Scripting
  • Verilog
  • VHDL
  • Python
  • ModelSim
  • Xilinx ISE
  • Synopsys/Cadence Tools

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