Publications in Refereed Journals


National Journals

  1. V. Kamakoti and C. Pandu Rangan, Efficient Transitive Reduction of Permutation Graphs and its Applications, Journal of Computer Science and Informatics Computer Society of India, Vol. 23, No. 3, pp. 52-59, 1993.

International Journals

  1. V. Kamakoti and C. Pandu Rangan, An Optimal Algorithm for Reconstructing a Binary Tree,Information Processing Letters, Vol. 42, pp. 113-115, 1992.
  2. K. Arvind, V. Kamakoti and C. Pandu Rangan, Efficient Parallel Algorithms for Permutation Graphs, Journal of Parallel and Distributed Computing, 26:116-124, 1995.
  3. V. Kamakoti, Kamala Krithivasan and C. Pandu Rangan, Efficient Randomized Algorithms for the Closest Pair Problem on Colored Point Sets, Nordic Journal of Computing, 2:28-40, 1995.
  4. T. Graf and V. Kamakoti, Sparse Dominance Queries for many points in Optimal time and Space, Information Processing Letters 64:287-291, 1997.
  5. Vr. Annamalai, C. S. Krishnamoorthy and V. Kamakoti, Adaptive Finite Element Analysis on a Parallel and Distributed Environment, Journal of Parallel Computing - Special Issue on High Performance Computing for Automotive Industries, pp. 1413-1434, 1999.
  6. V. Kamakoti and N. Balakrishnan, Efficient Randomized Algorithms for the Closest Pair Problem on Distributed Shared Memory Systems, International Journal of Mathematical Algorithms, Vol. 1, No. 2, pp. 81-105, 1999 [ISSN 1027-9350].
  7. L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid and V. Kamakoti, Pseudo-online testing methodologies for various components of field programmable gate arrays, Microprocessors and Microsystems, Vol. 29 (2005), pp. 99-119.
  8. K. Najeeb, Vishal Gupta, V. Kamakoti and Madhu Mutyam, Temporal Redundancy Based Encoding Technique for Power and Delay Reduction of On- Chip Buses, Journal of Low Power Electronics, Elsevier, Vol. 2, No. 3 (2006), pp. 425-436.
  9. V. R. Devanathan, C. P. Ravikumar and V. Kamakoti, On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores, Journal of Low Power Electronics, Vol. 2, No. 3 (2006), pp. 464-476.

2006

  1. K. Najeeb, P. Vishal Gupta, V. Kamakoti and V. Madhu Mutyam, Delay and Peak Power Minimization for On-Chip Buses using Temporal Redundancy, Proceedings of the 16th ACM SIGDA Great Lakes Symposium on VLSI Design, Philadelphia, USA, pp. 119-122, April 2006.
  2. Kavish Seth, K. N. Viswajith, S. Srinivasan and V. Kamakoti, Ultra Folded High-Speed Architectures for Reed-Solomon Decoders, Proceedings of the 19th IEEE/ACM-SIGDA International Conference on VLSI Design, January 2006, Hyderabad, India, pp. 517-520.
  3. Vivek Garg, Vikram Chandrasekhar, M. Sashikanth and V. Kamakoti, An Area and Configuration-bit optimized CLB Architecture and Timing-Driven Packing for FPGAs, To appear in the proceedings of IEEE/ACM SIGDA International Conference on VLSI Design, 2006, Hyderabad, India, pp. 507- 510.
  4. H. Siva Kumar Sastry, Shyam Shroff, S. K. Noor Mahammad and V. Kamakoti, Efficient Building Blocks for Reversible Sequential Circuit Circuit, Appeared in the Proceedings of the 49th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2006), Puerto Rico, August 2006.
  5. S. K. Noor Mahammad, H. Siva Kumar Sastry, Shyam Shroff and V. Kamakoti, Constructing Online Testable Circuits using Reversible Logic, Appeared in the Proceedings of the 10th IEEE VLSI Design and Test Symposium (VDAT), Goa, India, August 2006, pp. 373-383.
  6. Debi Prasad, Archana Rai, Karthik Venkatraman, Senthil Kumar, V Kamakoti, Kailasnath S Maneperambil and Vivekananda M Vedula, A Novel Unified Framework for Functional Verification of Processors using Constraint Solvers, Appeared in the Proceedings of the 10th IEEE VLSI Design and Test Symposium (VDAT), Goa, India, August 2006.
  7. V. R. Devanathan, C. P. Ravikumar and V. Kamakoti, On Reducing Transition Fault Test Time and Test Power for SOCs in Hierarchical Scan Test, Proceedings of the First International IEEE Design and Test workshop, Dubai, Nov. 2006.
  8. Saravanan, M., Ravindran, B., and Raman, S. (2006) " Improving Legal Document Summarization using Graphical Models " In the Proceedings of the Nineteenth Annual Conference on Legal Knowledge and Information Systems(JURIX 2006), pp. 51-60, IOS Press.
  9. Awasthi, P., Rao, D. G., and Ravindran, B. (2006) "Part Of Speech Tagging and Chunking with HMM and CRF". In the Proceedings of NLPAI Machine Learning Contest 2006 , Mumbai, India.
  10. Gagrani, A., Gupta, L., Ravindran, B., Das, S., Roychowdhury, P., and Panchal, V. K. (2006) "A Hierarchical approach to Landform Classification of Satellite Images using a Fusion Strategy". In the Proceedings of Fifth Indian Conference on Computer Vision, Graphics, and Image Processing (ICVGIP 2006).
  11. Saravanan, M., Raman, S., and Ravindran, B. (2006) "A Probabilistic Approach to Multi-Document Summarization for Generating a Tiled Summary". In International Journal of Computational Intelligence and Applications, Vol. 6, No. 2, June 2006, pp. 231-244. Imperial College Press. (This is an expanded version of the conference paper below.)

2005

  1. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, Detecting SEU-caused Routing Errors in SRAM-based FPGAs, Eighteenth International Conference on VLSI Design, January 2005, Kolkata, India, pp. 736-741.
  2. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, Cluster-based Detection of SEU-caused Errors in LUTs of SRAM-based FPGAs, Appeared in proceedings of the ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), January 2005, Shanghai, China, pp. 1200-1203.
  3. E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, Efficient Methodology for Detection and Correction of SEU-based Interconnect Errors in FPGAs using Partial Reconfiguration (Extended Abstract), Appeared in proceedings of the 13th ACM International Symposium on Field Programmable Gate Arrays, February 2005, Monterey, California, USA, pp. 265.
  4. E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-based FPGAs, Appeared in proceedings of the 12th Reconfigurable Architectures Workshop (RAW 2005), Colorado, USA.
  5. E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, A CLB architecture for Online correction of SEUbased Errors in LUTs of SRAM-based FPGAs, Appeared in the proceedings of the 10th European Test Symposium, (2005), Tallin.
  6. E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, Efficient Methodology for Detection and Correction of SEU-based Interconnect Errors in FPGAs using Partial Reconfiguration, Appeared in the proceedings of the 10th European Test Symposium, (2005), Tallin.
  7. Noor Mohammad, Vikram Chandrasekhar, V. Muralidharan and V. Kamakoti, Reduced Triple Modular Redundancy for Tolerating SEUs in SRAMbased FPGAs, Appeared in the proceedings of NASA International Conference on Military Applications in Programmable Logic Devices (MAPLD), September 2005, USA.
  8. CH. Sivasai Prasanna, N. Sudha, V. Kamakoti, A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation, Appeared in the Proceedings of 18th International Conference on VLSI Design, January 2005, Kolkata, India, pp. 795-798.
  9. R.Pradeep, S.Vinay, Sanjay Burman and V. Kamakoti, FPGA based agile algorithm-on-demand coprocessor, Appeared in proceedings of Design Automation and Test in Europe (DATE 2005), March 2005, Munich, Germany, pp. 82-83.
  10. R. Manimegalai, E. SivaSoumya, V. Muralidharan, B. Ravindran , D. Bhatia and V. Kamakoti , Placement and Routing for 3D-FPGAs using Reinforcement Learning and Support Vector Machines, Appeared in the Proceedings of 18th International Conference on VLSI Design, January 2005, Kolkata, India, pp. 451-456.
  11. Vivek Garg, Vikram Chandrasekhar, Sasikanth and V. Kamakoti, A Function Generator-based Reconfigurable System, Appeared in the proceedings of the IEEE/ACM SIGDA Asia South Pacific Design Automation Conference 2005 (ASPDAC), January 2005, Shanghai, China, pp. 905-909.
  12. Vivek Garg, Vikram Chandrasekhar, Sasikanth and V. Kamakoti, A Novel Packing Algorithm for CLB Area Reduction, Appeared in the proceedings of the IEEE/ACM SIGDA Asia South Pacific Design Automation Conference 2005 (ASPDAC), January 2005, Shanghai, China, pp. 791-794.
  13. K Uday Bhaskar, M Prasanth, G Chandramouli and V Kamakoti, A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip, Appeared in the Proceedings of 18th International Conference on VLSI Design, January 2005, Kolkata, India, pp. 207-212.
  14. K. Uday Bhaskar, M. Prashanth, V. Kamakoti and M. Kailasnath, A Framework for Automatic Assembly Program Generator (A2PG) for Functional Verification and Testing of Processor Cores, Appeared in the proceedings of the Asia Test Symposium (ATS), December 2005, Kolkata, India.
  15. Saravanan, M., Raman, S., and Ravindran, B. (2005) "A Probabilistic Approach to Multi-Document Summarization for generating a Tiled Summary". In the Proceedings of the International Conference of Computational Intelligence and Multimedia Applications (ICCIMA '05).
  16. Siva Soumya, E., Manimegalai, R., Muralidharan V., Ravindran, B., Kamaoti, V., and Bhatia, D. (2005) "Placement and Routing for 3D-FPGAs using Reinforcement Learning and Support Vector Machines". In the Proceedings of the Eighteenth International Conference on VLSI Design.
  17. Saravanan, M., Ravindran, B., and Raman, S. (2005) "A Review of Automatic Summarization". Presented in the Workshop on Optical character Recognition with workflow and Document Summarization, IIIT Allahabad, March 19-20.
  18. Saravanan, M., Ravindran, B., and Raman, S. (2005) "Learn to Teach Autistic Children". Presented in the National Conference on Computational Intelligence (St. Joseph's College, Trichy), Feb 16-18.

2004

  1. Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, Balakuteswar V. Voleti, A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation, 17th International Conference on VLSI Design, Mumbai, January 5-9, 2004, pp. 1071-1076.

  2. CH. Sivasai Prasanna, N. Sudha and V. Kamakoti, A Hardware-directed Face Recognition system based on Local Eigen Analysis with PCNN, Appeared in the proceedings of International Conference on Neuro Infrmation Processing (ICONIP), November 2004, Kolkata, India, pp. 327-332.
  3. A. Pavan Kumar, Sukhendu Das and V. Kamakoti, Face Recognition Using Weighted Modular Principle Component Analysis, Appeared in the proceedings of International Conference on Neuro-Information Processing (ICONIP), November 2004, Kolkata, India, pp. 362-367.
  4. A. Pavan Kumar, V. Kamakoti and Sukhendu Das, An Architecture for Real Time Face Recognition usingWMPCA, Appeared in the proceedings of Indian Conference on Computer Vision, Graphics and Image Processing (ICVGIP), December 2004, Kolkata, India, pp. 644-649.
  5. P. Pratibha, Siva Nageswara Rao Borra, A. Muthukaruppan, S. Suresh, and V. Kamakoti, ASPIRE: Automatic Spatial Partitioning in Reconfigurable Environments Using Genetic Algorithms, Mexican International Conference on Artificial Intelligence, Lecture Notes in Computer Science (LNCS 2972), Mexico City, April 2004, pp. 735-745.
  6. P. Subrahmanya, R. Manimegalai, V. Madhu Muthyam, V. Kamakoti, A Bus Encoding Technique for Power and Crosstalk minimization, 17th International Conference on VLSI Design, Mumbai, January 5-9, 2004, pp. 443-448.
  7. E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, A Novel CLB Architecture to Detect and Correct SEU in LUTs of SRAM-based FPGAs, Appeared in the Proceedings of IEEE International Conference on Field-Programmable Technology (FPT), December 2004, Brisbane, Australia, pp. 121-128.
  8. A. Manoj Kumar, Jayaram Bobba and V. Kamakoti, MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis, International Conference on Design Automation and Test in Europe, DATE 2004, Paris, France, February 2004, pp. 922-929.
  9. A. Manoj Kumar, Jayaram Bobba and V. Kamakoti, SHAPER: Synthesis for Hybrid FPGA Architectures containing PLA elements using Reconvergence Analysis - (Extended Abstract), Twelfth ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2004), Monterey, California, February 2004, pp. 251.
  10. R. Manimegalai, B. Jayaram, A. Manojkumar and V. Kamakoti, SHAPER:Synthesis for Hybrid FPGAs containing PLAs using Reconvergence Analysis Appeared in the proceedings of IEEE Field Programmable- Technology (FPT), December 2004, Brisbane, Australia.
  11. Manoj Kumar A, Jayaram Bobba, R. Manimegalai and V.Kamakoti, MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Arrays,11th Reconfigurable Architectures Workshop (RAW 2004), Santa Fe, New Mexico, USA, April 2004.
  12. K Uday Bhaskar, G Chandramouli and V Kamakoti, Pariksa- Functional Verification Tool for x86 Architecture, Appeared in the Proceedings of Eighth VLSI Design & Test Workshop (VDAT), August 2004, Mysore, India, pp. 492-502.
  13. Ravindran, B. and Barto, A. G. (2004) "Approximate Homomorphisms: A Framework for Non-exact Minimization in Markov Decision Processes". In the Proceedings of the Fifth International Conference on Knowledge Based Computer Systems (KBCS 04).
  14. Ravindran, B. (2004) "An Algebraic Approach to Abstraction in Reinforcement Learning". Doctoral Dissertation, Department of Computer Science, University of Massachusetts, Amherst MA.

2003

  1. P. Pratibha, Siva Nageswara Rao Borra, A. Muthukaruppan, S. Suresh, V. Kamakoti, An Enhanced Evolutionary Approach To Spatial Partitioning For Reconfigurable Environments, 2003 IEEE Congress on Evolutionary Computation, December 8-12, 2003, Canberra, Australia.
  2. M. Madhu, V. Srinivasa Murthy and V. Kamakoti, Dynamic Coding Technique For Low Power Data Bus, Proceedings of IEEE Computer Society Symposium on VLSI, (ISVLSI 2003), Tampa, Florida, USA, pp. 252-253.
  3. L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani and V. Kamakoti, Online Testing of Interconnect Faults in SRAM Based Reconfigurable Systems, Eighth IEEE European Test Workshop, (ETW 2003), The Netherlands.
  4. L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti and S. Suresh, Online location of Multiple Faults in LUT Based Reconfigurable Systems, International Conference on VLSI Design 2003, (VLSI 2003), Las Vegas, USA, June 23-26, 2003, pp. 224-232.
  5. L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid and V. Kamakoti, Testable Clock Routing Architecture for Field Programmable Gate Arrays, Thirteenth International Conference on Field Programmable Logic and Applications 2003, (FPL 2003), Lisbon, Portugal, Sept. 1-3, 2003, Lecture Notes in Computer Science (LNCS) vol. 2778, pp. 1044-1047.
  6. L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani and V. Kamakoti, A Novel Method for Online In-Place Detection and Location of Multiple Interconnect in SRAM Based FPGAs, The Twelfth Asian Test Symposium, November 17-19, 2003, Xian, China.
  7. Jayaram Bobba, A. Manoj Kumar and V. Kamakoti, Parallel Partitioning Techniques for Logic Minimization using Redundancy Identification, International Conference on High Performance Computing 2003, (HiPC 2003), Hyderabad, India, Dec. 17-20, 2003, pp. 174-183.
  8. Siva Nageswara Rao Borra, S. Suresh, A. Muthukaruppan and V. Kamakoti, A Parallel Genetic Approach to the Placement Problem for Field Programmable Gate Arrays, Tenth Reconfigurable Array Workshop, (RAW 2003), Nice, France, pp. 184.
  9. A. Muthukaruppan, S. Suresh and V. Kamakoti, A Novel Parallel Three Phase Genetic Approach to Routing for Field Programmable Gate Arrays, Proceedings of IEEE Field Programmable Technology 2003, Lecture Notes in Computer Science (LNCS) Vol. 2778, Hong Kong, pp. 336-339.
  10. P. Pratibha, Siva Nageswara Rao Borra, A. Muthukaruppan, S. Suresh, V. Ganesh and V. Kamakoti, A Parallel Evolutionary Approach to Spatial Partitioning in Reconfigurable Environments, Indian International Conference on Artificial Intelligence, Hyderabad, December 2003, pp. 938-951.
  11. Ravindran, B. and Barto, A. G. (2003) " Relativized Options: Choosing the Right Transformation". In the Proceedings of the Twentieth International Conference on Machine Learning(ICML 2003), pp. 608-615. AAAI Press.
  12. Ravindran, B. and Barto, A. G. (2003) " SMDP Homomorphisms: An Algebraic Approach to Abstraction in Semi Markov Decision Processes". In the Proceedings of the Eighteenth International Joint Conference on Artificial Intelligence (IJCAI 03), pp. 1011-1016. AAAI Press.
  13. Ravindran, B. and Barto, A. G. (2003) " An Algebraic Approach to Abstraction in Reinforcement Learning". In the Proceedings of the Twelfth Yale Workshop on Adaptive and Learning Systems, pp. 109-114. Yale University.

2002

  1. A. Muthukaruppan, S. Suresh, Siva Nageswara Rao Borra and V. Kamakoti, A Novel Three Phase Genetic Approach to Routing for Field Programmable Gate Arrays, Proceedings of Simulated Evolution And Learning 2002, Singapore, pp. 870-875.
  2. S. Suresh, A. Muthukaruppan and V. Kamakoti, A Novel Approach to Temporal Partitioning and Synthesis, Using an Evolutionary Algorithm Guided by ANN, for Reconfigurable Architectures, Artificial and Computational Intelligence 2002, Tokyo, Japan.
  3. A. Muthukaruppan, S. Suresh and V. Kamakoti, A Novel Evolutionary Approach to Routing for Field Programmable Gate Arrays, Artificial and Computational Intelligence 2002, Tokyo, Japan.
  4. A.Muthukaruppan, S.Suresh and V. Kamakoti, A Three Phase Approach to Routing for Field Programmable Gate Arrays, Proceedings of International Conference on Knowledge Based Computing Systems 2002 (KBCS2002), Mumbai, India. pp. 139-148.
  5. A. Muthukaruppan, S. Suresh and V. Kamakoti, A Novel Parallel Evolutionary Approach to Routing for Field Programmable Gate Arrays, Proceedings of International Symposium on Advanced Intelligent Systems 2002, Tsukuba, Japan.
  6. S. Suresh, A. Muthukaruppan and V. Kamakoti, A Parallel Genetic Approach to Temporal Partitioning And Synthesis for Reconfigurable Architectures, Proceedings of International Conference on High Performance Computing Asia 2002, Bangalore, India.
  7. S. Suresh, A. Muthukaruppan, Siva Nageswara Rao Borra and V. Kamakoti, An Artificial Neural Network Guided Parallel Genetic Approach to the Routing Problem for Field Programmable Gate Arrays, Proceedings of International Conference on Neural Information Processing 2002, Singapore, pp. 2645-2650.
  8. S. Suresh, A. Muthukaruppan and V. Kamakoti, A Parallel Genetic Approach, using Artificial Neural Networks, to Temporal Partitioning and Synthesis for Reconfigurable Architectures, Proceedings of International Conference on Soft Computing and Intelligent Systems 2002, Tsukuba, Japan.
  9. Ravindran, B. and Barto, A. G. (2002) " Model Minimization in Hierarchical Reinforcement Learning". In the Proceedings of the Fifth Symposium on Abstraction, Reformulation and Approximation (SARA 2002), pp.196-211, LNCS, Springer Verlag.

2001

  1. K. Srinathan, C. Pandu Rangan and V. Kamakoti, Toward Optimal Player Weights in Secured Distributed Protocols, Proceedings of Second International Conference on Cryptology, Lecture Notes in Computer Science (LNCS No. 2247), Springer Verlag, pp.232-241, Chennai, India, 2001. 1999
  2. Vr. Annamalai, C. S. Krishnamoorthy and V. Kamakoti, Mesh Generation on a Hypercomputing Environment, Presentation in Asia - Pacific Conference on Applied Mechanics, (APCOM 99), Singapore, December 1999. 1998
  3. T. Graf, V. Kamakoti, N. S. Janaki Latha and C. Pandu Rangan, The Colored Sector Search Tree: A Dynamic Data Structure for Efficient High Dimensional Nearest-Foreign-Neighbor Queries, Proceedings of the Fourth Annual International Computing and Combinatorics Conference (COCOON 98), held in Taipei, Taiwan, August 12-14, 1998.
  4. T. Graf and V. Kamakoti, Reducing Simple Polygons to Triangles - a proof for an Improved Conjecture, Proceedings of the International Colloqium on Automata, Languages and Programming (ICALP98), Denmark, July 13-17, 1998, Lecture Notes in Computer Science (LNCS), Springer Verlag, Vol. 1443, pp. 130-139, Kim G. Larsen, Sven Skyum, Glynn Winskel (eds.).
  5. T. Graf and V. Kamakoti, Optimal Algorithms for Computing Visible Foreign Neighbors among Colored Line Segments, Proceedings of the Sixth Scandinivian Workshop on Algorithmic Theory, (SWAT 98), Stockholm, Sweden, July 8-10, 1998, Lecture Notes in Computer Science, Springer Verlag, Vol. 1432, pp. 59-70.
  6. Ravindran, B. and Barto, A. G. (2001) " Symmetries and Model Minimization of Markov Decision Processes". Computer Science Technical Report 01-43, University of Massachusetts, Amherst, MA.

1997

  1. T. Graf, N. S. Janaki Latha, V. Kamakoti and C. Pandu Rangan, Optimal Parallel Algorithm for the all Nearest Foreign Neighbors Problem, Proceedings of the International Conference on High Performance Computing (HiPC), Bangalore, India, Dec 1997, IEEE press, pp. 132-136.
  2. V. Kamakoti and N. Balakrishnan, Efficient Algorithms for Prefix and General Prefix Computations on Distributed Shared Memory Systems with Applications, Proceedings of the International Conference on Parallel and Distributed Systems, Korea, Dec 1997, pp. 44-51, IEEE press.
  3. T. Graf, V. Kamakoti and N. Balakrishnan, Efficient Algorithm for the Nearest Neighbors Problem on Distributed Shared Memory Systems, Proceedings of the International Conference on High Performance Computing - Asia 1997, Seoul, Korea, April 1997, pp. 367-372, IEEE press.

1996

  1. V. Kamakoti and C. Pandu Rangan, Efficient Algorithm for testing the Adder and General Boolean Circuits using Randomization, Proceedings of the Fourth International Conference on Advanced Computing, Bangalore, Dec. 1996, pp. 100-107.
  2. V. Kamakoti and N. Balakrishnan, Efficient Algorithm for the Assignment Problem on Distributed Shared Memory Systems, Proceedings of the Fourth International Conference on Advanced Computing, Bangalore, Dec. 1996, pp. 44-51.

1995

  1. V. Kamakoti, Kamala Krithivasan and C. Pandu Rangan, Efficient Randomized Incremental Algorithm for the Closest Pair Problem using Leafary Trees, First Annual International Computing and Combinatorics Conference (COCOON 95), Xian, China, August 24-26, 1995, Lecture Notes in Computer Science (LNCS) No. 959, Springer Verlag, pp. 71-80.

1994

  1. P. Jagan Mohan, V. Kamakoti and C. Pandu Rangan, Efficient Randomized Parallel Algorithm for the Closest Pair Problem in D-Dimensions, Proceedings of the 13th World Computer Congress, Vol. 1. Hamburg, Germany, pp. 547 - 552, 1994.

1991

  1. V. Kamakoti et al, A Special Purpose Silicon Compiler for Designing Super Computing VLSI Systems, Proceedings of the 3rd NASA Symposium on VLSI Design, Moscow, USA, pp. 13.1.1 - 13.1.15, 1991.

Publications in Refereed National Conferences

1995

  1. V. Kamakoti, Dynamically Reconfigurable Fault-Tolerant Recursive VLSI Architecture, Proceedings of the First Fault-tolerant Computing Symposium, December 1995, IIT Madras.

1994

  1. R. Chandrasekhar, V. Kamakoti, R. Rajaraman, N. Venketeswaran and C. R. Visvanath, Dynamically Reconfigurable Fault-Tolerant VLSI Arrays, Proceedings of the Workshop on Real Time Embedded Computing Systems, Nov. 25-26, 1994, Association for Advancement of Fault-Tolerant and Autonomous Systems, Bangalore.