Register Here

For live Webcast: Click here


Welcome



RISC-V International Conference (2nd-3rd April 2017)

We welcome you to the first RISC-V International Conference to be held at IIT Madras on 2nd and 3rd April 2017. The conference aims to advance the use of RISC-V ISA based systems across all application domains and to provide a forum for various stakeholders to share their experiences. The conference will broadly focus on the RISC-V SoC sub-systems and domain specific issues.

SoC Eco-System: For the RISC-V ISA to be successful, an ecosystem rich in Cores, SoC fabrics, IP blocks, verification environments and validated backend processes is critical. This will be one of the key areas of this conference series. And in keeping with the open source narrative of RISC-V ISA, the conference will focus on open source SoC fabrics and IP blocks. Standardization around common SoC fabrics is especially key for low cost RISC-V based SoCs, since it helps reduce design and verification cycles.

Domains:

To help RISC-V based designs reach critical mass in specific verticals, the conference series will provide a platform for verticals to bring RISC-V based designs to maturity in those verticals. Currently the following vertical are targeted
  • SoC Fabrics
  • IP Blocks
  • Verification Environment
  • Physical Design Flow
  • HW and SW Security support
  • Low Power Systems
  • High Performance Computing
  • Safety Critical Systems
  • Storage Systems
This list represents the activity that has been observed in the RISC-V community and presumably will evolve over time. We realize that a single conference is not enough to drive a large number of verticals forward and plan to have BoF sessions to arrive at a consensus on how to drive verticals. We anticipate this will happen via dedicated working groups that will gravitate towards an independent existence.


Prof. V Kamakoti
Professor, Department of Computer Science & Engineering
Email: kama@cse.iitm.ac.in
Indian Institute of Technology, Madras

G S Madhusudan
Principal Scientist, Department of Computer Science & Engineering
Email: gs.madhusudan@cse.iitm.ac.in
Indian Institute of Technology, Madras


Venue ICSR Building
IIT-Madras Campus
Sardar Patel Road
Chennai, 600036
Tamil Nadu, India
Map
Directions From Airport
From Central Railway Station
Accommodation options The Westin
154 Velachery Main Road, Chennai
Contact: 044 6633 3777
Map

Ginger
No 1 FA, 11th Floor, IITM Research Park, Taramani, Chennai
Contact: 044 6666 3333
Map
Lemon Tree
72, Sardar Patel Rd, Venkta Puram, Guindy, Chennai
Contact:+91 44 4423 2323
Map

Raj Palace Sundar
12, Durgabai Deshmukh Road, Raja Annamalai Puram, Adyar, Chennai
Contact:+91 44 2464 1234
Map

ITC Grand Chola
Little Mount, Guindy, Chennai, Tamil Nadu 600032
Contact:+91 44 2220 0000
Map

Travel and Sightseeing: Chennai offers a host of options ranging from the ancient city of Mahabalipuram, Museums focused on Indian antiquities and some of the best beaches around, if you just want to catch the sun. For the more adventurous, sailing, surfing and scuba diving facilities are also available

Technical Program Committee


Rick O' Connor (Chairman)
Krste Asanovic
V Kamakoti
G S Madhusudan
Preeti Ranjan Panda
Mainak Chaudhuri

Organizing Committee


Prof. V Kamakoti (Chairman)
G.S. Madhusudan
M J Shankararaman
V S Vasan
K S Venkataraghavan
Neel Gala
Rahul Bodduna
Arjun Menon
Abhinaya Agrawal
Vinod G

Chowdhary Musunuri
Title: RISC-V core as a soft processor in FPGAs
Abstract -
Soft processors are often used in field programmable gate array (FPGA) implementations. Soft processors can be combined with custom peripherals and logic to create a system level design that is purpose built in a single FPGA device. Having a soft processor with an eco-system around it helps engineers partition, implement and optimize designs for most optimal performance. In this keynote, I will talk about using RV32IM RISC-V core as a soft processor in FPGAs. I will also talk about the ecosystem that is around RV32IM RISC-V core that helps FPGA engineers implement secure, reliable and power optimized designs in FPGAs.
Bio – Chowdhary Musunuri serves as Senior Director, Solutions & Applications for Microsemi. He has been working for Microsemi India since September 2012. Chowdhary has more than 20 years of experience in systems engineering and product development. Prior to joining Microsemi India, Chowdhary was a senior manager, R&D at Cisco Systems, San Jose where he built Cisco Telepresence audio/video codecs and high end video conferencing systems. He also held senior technical positions at IP video systems, an early start up in the bay area and at National Semiconductors (now TI). Chowdhary holds a master’s degree in Electrical & Electronics Engineering from Arizona State University, USA.


G.H. Rao
Bio -
GH Rao (or “GH” as he is called) is a corporate officer of HCL Technologies. He currently heads the Engineering and R&D Services (ERS) practice at HCL that focuses on providing product and platform engineering services to leading OEMs, Tier 1s, ISVs and Enterprises globally. As a business head, he manages the 21000+ strong engineering team servicing customers across domains like Aerospace, Automotive, Consumer Electronics, Industrial Manufacturing, ISVs, Medical devices, Servers & storage, Semiconductor and Telecom. An engineer by education, GH joined HCL as a R&D engineer in 1980. GH was part of the HCL’s R&D team that developed Hardware subsystems for a range of micro/mini computers. He was the chief architect of the Multiprocessor systems employing contemporary architectures for a range of high-end minicomputers launched by HCL during late 1980s. Later when HCL and Hewlett Packard formed a joint venture (HCL-HP) in the early 90s, GH was heading the technology adaptation and engineering teams. GH has been instrumental in building Test/compliance labs and Teardown labs at HCL, a unique in Indian private Industry, which has enabled HCL to offer comprehensive Concept to Manufacturing solutions (C2M) to leading OEMs and Tier 1s.GH travels extensively to meet customers globally and is a member of NASSCOM Engineering Services steering committee. GH holds a bachelor’s degree in Electronics and Communication Engineering


Rick O'Connor
Title: RISC-V Going Mainstream
Abstract:
The free and open RISC-V Instruction Set Architecture (ISA) began development at UC Berkeley in 2010, with the frozen base user ISA specification released in May 2014, and has since seen rapid uptake around the globe, including the first commercial shipments. The RISC-V effort distills over 30 years of processor research at UC Berkeley and elsewhere into an extensible instruction set that can be fully customized. This talk will cover features of RISC-V ISA design, which has the goals of scaling from deeply embedded implementations for IoT up to the largest warehouse-scale computers, with support for extensive customization. We'll also detail the uptake of RISC-V globally and the development of the RISC-V ecosystem, including the non-profit RISC-V Foundation.

Bio – Rick O'Connor is Executive Director of the non-profit RISC-V Foundation. RISC-V is a new instruction set architecture that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. Rick is also Executive Director of RapidIO.org, a non-profit consortium controlled by its numbers, which directs the future development and drives the adoption of RapidIO, the "unified fabric for performance critical computing". With many years of executive management experience in semiconductor and systems companies, Rick possesses a unique combination of business and technical skills and over his career, was responsible for the development of dozens of products accounting for over $500 million in revenues. Rick holds an Executive MBA from the University of Ottawa and is an honors graduate of the faculty of Electronics Engineering Technology at Algonquin College.


Nikhil Rishiyur
Title: Verification and Debugging for High-Assurance RISC-V
Abstract:
- In this talk Nikhil will provide a brief overview of several techniques in use for high assurance of RISC-V CPUs and Systems:

  • Correct-by-Construction
  • Direct remote GDB
  • Tandem Verification
  • Seamless FPGA acceleration
  • BlueCheck (hardware QuickCheck) automated testing
  • Formal Models and Proofs of CPUs and Memory Systems
We also demonstrate many of these techniques in an adjunct session of this conference.


Smruti Sarangi
Title: Tejas Architectural Simulator
Abstract:
Over the years RISC-V has become a very prominent ISA in the open source hardware community. There is a growing movement around RISC-V, and now there is a lot of effort in developing tools, and operating systems for RISC-V based systems. The open source RISC-V hardware community has several projects for developing full fledged RISC-V based processors. There is an urgent need for an architectural simulation platform for such projects. We propose the use of the Tejas architectural simulator. Tejas is a cycle accurate, fully featured, JAVA based simulator that has been benchmarked against native hardware. It can simulate a host of processors including complex OOO processors and GPUs for performance, and power. We shall describe the potential uses of Tejas in a RISC-V processor development effort, and how it can be used to accelerate a RISC-V processor development effort.

Bio - Smruti Ranjan Sarangi is an Assistant Professor in the computer science and engineering department at IIT Delhi since January 2011. He primarily works in parallel and distributed architectures and systems. His research areas cover multicore processors, networks on chip, operating systems for parallel computers, and parallel algorithms. His book on computer architecture, "Computer Organisation and Architecture" is due to be released by McGrawHill India in the third week of July, 2014. Click this link to read more about the book. Dr. Sarangi obtained his Ph.D in computer architecture from the University of Illinois at Urbana Champaign(UIUC), USA in 2006, and a B.Tech in computer science from IIT Kharagpur in 2002. After completing his Ph.D he has worked in Synopsys Research, and IBM Research Labs. He has filed five US patents and has published 34 papers in reputed international conferences and journals,. Dr. Sarangi has been awarded the MICRO (International Symposium on Micro-Architecture) best paper award for his work. His work has featured in the MIT Technology Review and on popular technology sites like theregister and slashdot. He has also won the teaching excellence award at IIT Delhi in 2014.


Prem Kumar Arora
Title: Microsemi's Roadmap with RISC-V
Abstract:
This talk will elaborate on the history of Microsemi, the SoC and FPGA group and further elaborate on the applications spaces that it operates in. He will also discuss about how RISC V fits into the key verticals that form the core basis of Microsemi’s business. His talk will focus on the synergies derived from having a roadmap that includes RISC V in the roadmap including the advantages in security and reliability.

Bio – Prem Kumar Arora is the Director of Marketing, SoC and FPGA group at Microsemi. His responsibilities include product management, solutions engineering, eco-system and partner development. Prior to his current role at Microsemi, Prem was the group manager of wireless products at Cypress Semiconductor. Prem holds a BE in Electronics and Communication Engineering and is an alumni of INSEAD.


Mainak Chaudhuri
Title: Addressing Performance issues of SRAM and DRAM caches
Abstract:
Server processors are designed to deliver high throughput at low latency. As a result, these processors are usually equipped with a few tens of latency-optimized compute engines or processing cores.Meeting the instruction and data demand of these cores requires a deep cache hierarchy between the compute engines and the main memory. The last level of the on-die SRAM cache hierarchy and the memory-side DRAM cache have lately attracted significant attention from the researchers as well as industry design teams. In this talk, I will discuss some of the important performance issues in the design of the on-die last-level SRAM cache and the memory-side DRAM cache. In particular, optimization of hit latency and miss count for the on-die last-level SRAM cache and efficient maintenance of coherence information across the on-die cache hierarchy will be discussed. For the memory-side DRAM cache, I will touch upon the fundamental trade-offs between hit rate and bandwidth optimization and discuss a few techniques to improve the bandwidth delivery in systems equipped with such caches.

Bio - Mainak has done his Bachelor's of Technology from IIT-Kharagpur in 1999. He completed his Masters and PhD from Cornell in 2001 and 2004 respectively. He is currently an associate professor at IIT-Kanpur in the Dept. of Computer Science and Engineering. His research interests include Computer Architecture and has published many papers in reputed international conferences and journals.


Alex Bradbury
Abstract:
The lowRISC platform aims to be the “Linux of the hardware world”, providing a high quality, secure, and open base for derivative designs. Our goal is to lower the barrier of entry to producing custom silicon, establishing a vibrant ecosystem around secure and open hardware designs. lowRISC was formed as a not-for-profit community-driven organisation to pursue these aims. This talk will explore our current status and roadmap, describing our novel platform features such as tagged memory and minion cores. More information: http://lowrisc.org

Bio

Live webcast will begin on Sunday, April 2nd, 9:00 AM IST