Faculty Members

Senior Project Members


List of Current Students

Current PhD Students
Name Email Guide Category Extension Research Area
Joseph H. R. Isaac joehrisaac@gmail.com Dr. B. Ravindran Full Time 5390 Virtual Reality and Augmented Reality
Sudarsun Santhiappan sudarsun@gmail.com Dr. B. Ravindran Full Time 5390 Machine Learning
D Anthony Balaraju balaraju17@gmail.com Dr. Chester Rebeiro Full Time 5390 Secure Hardware
Sanjay Burman sanjayburman@gmail.com Prof. V. Kamakoti External - Secure Systems Engineering
Abhijit Pradhan - Prof. V. Kamakoti (+Prof. Hema murthy) External - Low bit error coding for speech
P. L. S. K. Patanjali patanjali.slpsk@gmail.com Prof. V. Kamakoti Full Time 5390 Probabilistic Computing for Low Power Design
M Sudhakar msudhakar.india@gmail.com Prof. V. Kamakoti Part Time - Network Architectures
Prasanna Karthik vprasannakarthik@gmail.com Prof. V. Kamakoti Full Time 5375 Secure Computer Architecture
Sareena K P sareena.kp@gmail.com Prof. V. Kamakoti Full Time 5375 Network Architecture
Gargi Mitra netlab1stfeb@gmail.com Prof. V. Kamakoti(+Dr. Nitin Chandrachoodan (Dept. of EE)) Full Time 5375 Network Security and Privacy, Blockchain Technology
Sarath Kumar Kodiyalam - Prof. V. Kamakoti Full Time 5390 Storage Architecture
S Ranjani - Prof. V. Kamakoti External - Embedded Systems
P. Kandaswamy - Prof. V. Kamakoti - - -
Current MS Students
Name Email Guide Category Extension Research Area
Subhojyoti Mukherjee subhojyotimukherjee22@gmail.com Dr. B. Ravindran HTRA 5390 Reinforcement Learning
Priyesh Vijayan priyesh@hotmail.co.in Dr. B. Ravindran Project 5390 Deep learning and Social networks
Gnanambikai Krishnakumar gnanukrishna@gmail.com Dr. Chester Rebeiro Full Time 5390 Hardware security
Ahana Chatterjee ahanacttrj@gmail.com Prof. V. Kamakoti Full Time 5390 Embedded System
Prathamesh Deshpande prathameshsdeshpande@gmail.com Dr. S. Balachandran Full Time 5390 Data Mining
Deepak Mittal deepak242424@gmail.com Dr. B. Ravindran Full Time 5390 Deep Learning and Machine Learning
Arjun Menon c.arjunmenon@gmail.com Prof. V. Kamakoti Project 5390 Secure Computer Architecture
Vikas Chauhan vikaschauhan917@gmail.com Prof. V. Kamakoti HTRA 5390 High Level Synthesis using ADDs
Arnab Roy aryya4u@gmail.com Prof. V. Kamakoti HTRA 5390 Neuromorphic Computing
Pavan Torvi - Prof. V. Kamakoti External - -
G Swarnavaray swarnavaray@anurag.drdo.in Prof. V. Kamakoti Part Time 5390 Formal Verification of Operating System Microkernels
Rahul Bodduna - Prof. V. Kamakoti - - Multi core architectures
V. Gokulkrishnan - Prof. V. Kamakoti(+Nitin Chandrachoodan) - - -
G. Vinod - Prof. V. Kamakoti - - Compuetr Architecture
Current M.Tech Students
Name Email Guide Category Extension Project Title/Domain
Madhur Charkha madhur.charkha@gmail.com Dr. B. Ravindran Full Time 5390 Social Network Analysis

List of Former Students

Former PhD Students
Name Email Guide Graduation Year Thesis Title
K. Najeeb k.najeeb@gmail.com Prof. V. Kamakoti 2007 Peak Dynamic Power Issues in Digital Circuit Design
R. Manimegalai mmegalai@yahoo.com Prof. V. Kamakoti 2007 Efficient Logic Synthesis and Placement for modern FPGA architectures
V. R. Devanathan vrd@ti.com Prof. V. Kamakoti 2007 On Power Safe Testing of System-on-Chips
Noor Mahammad noorse@gmail.com Prof. V. Kamakoti 2009 Novel Fault Tolerant Reconfigurable Architectures
Kavish Seth kavish@atheras.com Prof. V. Kamakoti(+Prof. S. Srinivasan) 2011 Efficient Motion Vector Recovery and Motion Estimation Schemes for H.264 Coded Video Streams
K. Shyamala prkshyamala@gmail.com Prof. V. Kamakoti 2013 Power, Area and Performance optimization techniques for Lookup Table based FPGAs
S. Srinivasan srinis@iitm.ac.in Prof. V. Kamakoti 2014 Studies on Border Length Minimization and Quadratic Assignment problems
Seetal Potluri potluri6@gmail.com Prof. V. Kamakoti(+Dr. Nitin Chandrachoodan) 2014 Power: Its Manifestations in Digital Systems Testing
Biswabandan Panda biswa.uce@gmail.com Dr. S. Balachandran 2015 Managing Hardware Prefetchers for Multi-core Systems
M. J. Shankar Raman mjsraman@gmail.com Prof. V. Kamakoti (+Dr. Gaurav Raina) 2016 Green Communication, Power-aware methodologies for the Internet
Neel Gala neelgala@gmail.com Prof. V. Kamakoti 2016 Emerging Computing Techniques for Low Power Error Resilient Design
Former MS Students
Name Email Guide Graduation Year Thesis Title
L. Kalyan Kumar kalyan.kumar.lakkavarapukota@intel.com Prof. V. Kamakoti 2003 Pseudo Online Testing Methodologies for Various Components of Field Programmable Gate Arrays
Siva Nageswara Rao Borra - Prof. V. Kamakoti 2003 Partitioning, Placement and Routing Algorithms for Field Programmable Gate Arrays
K Uday Bhaskar - Prof. V. Kamakoti 2006 Automatic Assembly Program Generation for functional Verification and Testing of Processor - Based Architectures
A Pavan Kumar a.pavankumar@yahoo.com Prof. V. Kamakoti(+Dr. Sukhendu Das) 2006 A WMPCA-based Face Recognition System on Programmable Chip
Chakka Siva Sai Prasanna - Prof. V. Kamakoti(+Dr. N. Sudha) 2006 An Area-Time Efficient VLSI Architecture for Eigenface-based Recognition System
Vivek Garg vivekgarg330@gmail.com Prof. V. Kamakoti 2006 Boolean Function Generation based Reconfigurable Architectures and Associated Packing Techniques
E. Syama Sundara Reddy syam506@yahoo.co.in Prof. V. Kamakoti 2007 Novel CLB Architectures and Techniques to Mitigate SEU Faults in SRAM-based FPGAs
J. Lavanya - Prof. V. Kamakoti 2010 On Test and Diagnostic Methodologies for Nanometer Technologies
Gomathi Rajan vgriit@gmail.com Prof. V. Kamakoti(+Dr. Thillairajan) 2010 Development of an Economic High Performance Storage Solution
Kunal K. Korgaonkar kunal.korgaonkar@gmail.com Prof. V. Kamakoti 2011 Reconstructing Transactional Memory: Fast Unbound Conflict Detection and Conflict-Graph based Contention Management
R. Karthik Raghavan kathrags@gmail.com Prof. V. Kamakoti 2011 ROSY: Exploring Life After Microarchitectural Death
Sajin Koroth sajinkoroth@gmail.com Dr. S. Balachandran 2011 Study on Hierarchical Floorpans of Order k
Anish Kumar ask.anish@gmail.com Prof. V. Kamakoti 2012 Performance driven Buffer Sizing technique for Network-on-Chips
V. Ashwin weashwin@gmail.com Prof. V. Kamakoti(+Dr. R. Manivasakan) 2012 Synthesis, Testing and Diagnosis of Reversible Logic Circuits
M. Pawan Kumar mpkpawan07@gmail.com Prof. V. Kamakoti 2012 Reliability-Aware Mapping and Placement of Network-on-Chips onto 3D ICs
Pradyot K V N kvnpradyot@gmail.com Dr. B. Ravindran 2013 Beyond Rewards : Learning from Richer Supervision
L. Srivani lsrivani@gmail.com Prof. V. Kamakoti 2013 Synthetic Benchmark Circuits for Accelerated Life Testing of FPGAs
Gandhi Virat Bhadresh ce.vbgandhi@gmail.com Prof. V. Kamakoti 2013 Dynamic Control of Power and Temperature in CMOS VLSI Circuits at ISO-Performance Conditions
Rangadurai Karthick R ranga1729@gmail.com Dr. B. Ravindran 2014 Sequence Modelling to Detect Network Intrusions
S. V. S. Suresh - Prof. V. Kamakoti(+Prof. R. Krishnakumar) 2014 Portable, Low Cost Five Lead Wireless ECG Device
Sathya Narayanan.N sathya281@gmail.com Prof. V. Kamakoti 2016 Proactive Channel Allocation MAC Protocols for Cognitive Radio Networks
Former M.Tech-Degree awarded
Name Email Guide Graduation Year Thesis Title
T.B.N. Ambedkar nrusimha@gmail.com Prof. V. Kamakoti 2002 UDP Level Dynamic Power Estimation and Location of Power Hungry Nets
John Prakash John jpj_04@yahoo.com Ptrof. V. Kamakoti 2002 Circuit Partitioning Based Don’t Care Identification
S. Krishna Kumar om_skkumar@yahoo.com Prof. V. Kamakoti 2002 Mapping of Logic Circuits To CPLD and LUT Based Hybrid FPGA Architecture
Venugopal Naik hello2venu@yahoo.co.in Prof. V. Kamakoti 2002 Logic Synthesis for FPGAs Using Embedded Memory Blocks
Anjana K. R anjanakr@hotmail.com Prof. V. Kamakoti 2004 A Synthesizable RTL model of an Instruction Decoder for the Intel x86 Core
Bhargavi R bhargaviren@hotmail.com Prof. V. Kamakoti 2004 A Synthesizable RTL model of Context Infrastructure of the Intel x86 Core
Shankar Umapathi - Prof. V. Kamakoti 2004 Automatic Assembly Program Generator for Hierarchical Descriptions of Processor Cores
Chandramouli G mouli_iit@yahoo.com Prof. V. Kamakoti 2004 A Synthesizable RTL Model of the Decoder Unit of the Intel x86 Core
Murali Rajagopalan - Prof. V. Kamakoti 2004 A Synthesizable RTL model of the Control Unit of the Intel x86 Core
Pradeepkumar S - Prof. V. Kamakoti 2004 A Synthesizable RTL model of an Arithmetic and Logic Unit of the Intel x86 Core
V. K. Padhmanabhan - Prof. V. Kamakoti 2004 Functional Verification using Automatic Assembly Program Generator for Processors
Ravi Yelamarthy yelamarthy_ravi@yahoo.com Prof. V. Kamakoti 2005 A Synthesizable RTL Model of an Arithmetic Logic Unit(MMX, SSE INTEGER INSTRUCTIONS) of the Intel x86 Core
Rajkumar G - Prof. V. Kamakoti 2005 A Synthesizable RTL Model of Floating Point Arithmetic and Logic Unit of the Intel x86 Core
Maruthi Rao K maruthi20@yahoo.com Prof. V. Kamakoti 2005 Verification of Integer and MMX units of the Intel x86 Core
Mahesh Kumar E S - Prof. V. Kamakoti 2005 A Synthesizable RTL Model of Control Unit of the Intel x86 Core
Ratna Kumar A ratnakumar_a@yahoo.com Prof. V. Kamakoti 2005 A Synthesizable RTL Model of Context Infrastructure and SSE2 of ALU of the Intel x86 Functional Model
Tinto James tintojames@yahoo.co.in Prof. V. Kamakoti 2005 A Synthesizable RTL Model of an Instruction Decoder for the Intel x86 Core
Ramesh Balan rbalan66@rediffmail.com Prof. V. Kamakoti 2005 Design and Implementation of Random Bit Generators in Hardware
Rahul Mallik mallikradhul@rediffmail.com Prof. V. Kamakoti 2005 Implementation of Cryptographic Algorithms in Hardware
Vinay Saripalli s.vinay@yahoo.com Prof. V. Kamakoti 2005 Agile Algorithm-on-Demand CO-Processor
Prashant Mangalagiri - Prof. V. Kamakoti 2005 Automatic Assembly Program Generator for Verification of Processor Cores
V.Karthik Venkataraman vkarthik.ee@gmail.com Prof. V. Kamakoti 2006 Test Pattern Generation for Branch Predictor of a Superscalar Microprocessor Architecture using Constraint Solvers
K. Senthil Kumar - Prof. V. Kamakoti 2006 Test Pattern Generation for Translation Lookaside Buffer of a Superscalar Microprocessor Architecture using Constraint Solvers
Archana Rai raiarchana_26@rediffmail.com Prof. V. Kamakoti 2006 Test Pattern Generation for Superscalar Processor: Reservation Station, Execution Unit and the Integration , using Constraint solvers
Debi Prasad Mohapatra hello_debi@yahoo.com Prof. V. Kamakoti 2006 Test Pattern Generation for Superscalar Processor: Cache, Register file and CDB Units, Using Constraint Solvers
Ramaprasad. K itsramprasad@gmail.com Prof. V. Kamakoti 2006 Memory Management Unit for the x86
E. Ramulu ramu_enugurthi@yahoo.com Prof. V. Kamakoti 2006 A Synthesizable RTL Model of FP ALU & Context Infrastructure of x86 Core
B.Praveen praveenb.mails@gmail.com Prof. V. Kamakoti 2006 A Synthesizable RTL Model of SSE,SSE2 and SSE3 ALU’s for INTEL x86 Core
NVV Satya Suresh Chowta suresh_chowta@yahoo.com Prof. V. Kamakoti 2006 Automatic Spatial Partitioning In Reconfigurable Environments
S. Nippan Kumar Reddy singamnipun@gmail.com Prof. V. Kamakoti 2006 Synthesis and Verification of INTEL x86 Core
M. Pradeep pradeep134@gmail.com Prof. V. Kamakoti 2006 A Synthesizable RTL Model of Control Unit for the INTEL x86 Core
P. N. Naveen Kumar pn_naveen38@yahoo.com Prof. V. Kamakoti 2006 A Synthesizable RTL Model of Exception Unit for the INTEL x86 Core
K.Bala Raju balarjuk507@yahoo.co.in Prof. V. Kamakoti 2006 A Synthesizable RTL Model of Exception Handling for x86
Pradeep Kumar - Prof. V. Kamakoti 2006 Development of Reconfigurable Agile Co-processor
Wg Cdr G Ananth anan_gv70@yahoo.com Prof. V. Kamakoti 2006 Kernel Development for a FPGA Based Reconfigurable Agile Co-processor
US.Karthikeyan us_karthi@yahoo.com Prof. V. Kamakoti 2006 Design of Programmable Interconnect Fabric for Multi FPGA Architecture
Poonam Gawade poonam_162@yahoo.co.in Prof. V. Kamakoti 2007 Digitized True Random Number Generator using Ring Oscillators in FPGA
Aditya Raturi - Prof. V. Kamakoti 2007 An Agile Co-Procesor
Chandra Sekhar Yapara chandrasekhar_yapara@yahoo.com Prof. V. Kamakoti 2007 Control Transfer Instruction Design and Validation on the India Processor
Vidyavati S Nayak - Prof. V. Kamakoti 2007 Packet Processing Algorithms for Hardware Implementations
Praveen Kumar D praveen_d_21@yahoo.com Prof. V. Kamakoti 2007 Design of a Generic Test Bed and Verification of Sequencer
Ashish Netam ashishnetam@gmail.com Prof. V. Kamakoti 2007 Creation of Automatic Verification Environment
Venkatachalam Janarthanan - Prof. V. Kamakoti 2007 Performance Analysis of Sequential Work loads on LVM managed filesystems in EVMS environment
Valliappan Ramasamy vramasamy@inautix.co.in Prof. V. Kamakoti 2007 Enterprise Volume Management System for RAID 5.0 Array
Rajesh Thangamani - Prof. V. Kamakoti 2007 Understanding Enterprise Volume Management System in Linux and Performance Analysis of Sequential Workloads for a RAID 1.0 Array
Mohammaed Shoaib shoaib.maks@gmail.com Prof. V. Kamakoti 2008 Concepts in Reliable and Optimal Systems Design
Virendra Kumar Patidar virendrakumarpatidar@gmail.com Prof. V. Kamakoti 2008 Sequential Test Power Reduction using Integrated Scan Cell and Test Vector Reordering Techniques
V. V. Narayana Rao venkatnarayana.rao@gmail.com Prof. V. Kamakoti 2008 Double Tree Scan (DTS) Architecture for Shift Power Reduction in Scan Testing
Dinesh Moparthi dinesh.m123@gmail.com Prof. V. Kamakoti 2008 A Simulation Study of Energy Efficient MAC Protocol in Wireless Sensor Network
Santhosh Kumar K S santhosh.sabawat@gmail.com Prof. V. Kamakoti 2008 A Simulation Study of Energy Efficient Protocol in Wireless Sensor Network
Umashankar Balasubramaniam - Prof. V. Kamakoti 2008 Wireless Sensor Network Solution for Data Center Environment Monitoring
Sumit Samajpati sumit.samajpati@gmail.com Prof. V. Kamakoti 2008 Creation of Automatic Verification Environment
Vankudothu Basha bashanaik@gmail.com Prof. V. Kamakoti 2008 Hardware Implementation for Pattern Matching
Veerendra Kumar Niddapu viru_myindia@yahoo.com Prof. V. Kamakoti 2008 Implementation and Evaluating the Performance of Snapshot Techniques
Chaudhari Parag Bhaskar paragbchaudhari@gmail.com Prof. V. Kamakoti 2008 Modeling and Simulation of ATM Traffic Congestion Control
Soumya Dev Poriya soumyadev.poriya@gmail.com Prof. V. Kamakoti 2008 Design and Implementation of a Pattern Matching Hardware based on Artificial Neural Network
Deepak Tomar Prof. V. Kamakoti 2010 Area and Power Analysis of Transactional Access Table based Hardware Transactional Memory
Pradeep Jasti Prof. V. Kamakoti 2010 Design Verification of Digital Circuits using High-level HDL
Suchith Rajagopal Prof. V. Kamakoti 2010 Air-borne Radar clutter simulation and signal processing using graphics processing unit
Gaurav Kumar Jain Prof. V. Kamakoti 2010 Integer arithmetic and logic unit of ANUPAMA in Bluespec
Suresh Pakkala Prof. V. Kamakoti 2010 Design of a Floating point unit for a 32-bit RISC processor-ANUPAMA
Aklesh Jain Prof. V. Kamakoti 2010 Similarity based error concealment method for block-based coded images
Hema Venkata Krishna Giri Narra Prof. V. Kamakoti 2011 Generating Synthetic Benchmark Circuits for Stress Testing FPGAS usin Particle Swarm Optimization
Shankar Ganesh Ramasubramanian Prof. V. Kamakoti 2011 Using Genetic Algorithm to generate Synthetic Benchmark Circuits to stress test FPGAs
John C.James Prof. V. Kamakoti 2011 Performance Enhancement of SONAR Data Processing using CUDA Framework
K. Sathish Kumar Prof. V. Kamakoti 2011 Performance Enhancement of Processes related to SONAR Data using CUDA Framework
Abhinav Narain Prof. V. Kamakoti 2011 Processing Large Scale Data for Prediction using Cloud Technology
Mahesh Kopp Prof. V. Kamakoti 2011 Parallel Processing System for Synthetic Aperture Radar Image Formation using GPU