Publications 2007

  1. N. Sudha,CH Siva Sai Prasanna and V. Kamakoti,An Efficient Digital Architecture for Principal Component Neural Network and its FPGA Implementation, IETE Journal of Research, Vol. 53. No. 5, pp. 425-432, Sept-Oct 2007.
  2. Siva Nageswara Rao Borra, Annamalai Muthukaruppan, S. Suresh and V. Kamakoti, A Novel Approach to The Placement and Routing Problems for Field Programmable Gate Arrays, International Journal on Applied Soft Computing, (7) 2007, pp. 455-470.
  3. A. Pavan Kumar, V. Kamakoti and Sukhendu Das, System-on- Programmable-Chip for Face Recognition using WMPCA, Pattern Recognition Letters, 28 (2007), pp. 342-349.
  4. V. R. Devanathan, C. P. Ravikumar and V. Kamakoti,Variation-Tolerant, Power-Safe Pattern Generation and Optimization framework, IEEE Design and Test of Computers, vol. 24, no. 4, pp. 374-384, Jul - Aug 2007.
  5. K. Najeeb, Karthik Gururaj, V. Kamakoti and Vivekananda M. Vedula, Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits, Journal of Low Power Electronics Vol. 3 No. 3, pp.280-292, 2007.
  6. V.R. Devanathan, C.P. Ravikumar, and V. Kamakoti, A Stochastic Pattern Generation and Optimization Framework for Variation-Tolerant, Power-Safe Scan Test, Proceedings of the International Test Conference, October 2007, Santa Clara, USA, paper 13.1.
  7. V.R. Devanathan, C.P. Ravikumar, and V. Kamakoti, PMScan : A Power- Managed Scan for Simultaneous Reduction of Dynamic and Leakage Power During Scan Test Proceedings of the International Test Conference, October 2007, Santa Clara, USA, paper 13.2.
  8. K. Najeeb, Vishnu Vardhan reddy, Siva Kumar Sastry Hari, V. Kamakoti and Vivekananda Vedula, Power Virus generation using behavioral models, Proceedings of the VLSI Test Symposium (VTS) 2007, Berkeley, California, USA, pp. 35-42.
  9. V. R. Devanathan, C. P. Ravikumar and V. Kamakoti, Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test, Proceedings of the VLSI Test Symposium (VTS) 2007, Berkeley, California, USA, pp. 167-172.
  10. V. R. Devanathan, C. P. Ravikumar and V. Kamakoti, On Power-Profiling and Pattern Generation for Power-Safe Scan Tests, Proceedings of IEEE Design Automation and Test in Europe (DATE), 2007, Nice, France, pp. 1-6.
  11. K. Vinay, Ratan Singh, S. Maleka, V. Kamakoti and Anirban Rahut, Delay Clock Methodologies for Timing-performance improvements of designs on FPGAs, Proceedings of the 11th IEEE VLSI Design and Test Symposium, August 8-11, Kolkata, India, 2007.
  12. K. Najeeb, Karthik Gururaj, V. Kamakoti and Vivekananda M. Vedula, Controllability Driven Power Virus Generation for Digital Circuits, Appeared in the proceedings of the International Conference on VLSI Design, 2007, Bangalore, India, pp. 407-412.
  13. V. R. Devanathan, C. P. Ravikumar and V. Kamakoti, Reducing SoC Test Time and Test Power in Hierarchical Scan Test: Scan Architecture and Algorithms, Appeared in the proceedings of the International Conference on VLSI Design, 2007, Bangalore, India, pp. 351-356.
  14. Shoaib Mohammad, Noor Mohammad and V. Kamakoti, A Genetic Approach to Gateless Custom VLSI Design Flow, Accepted for presentation in the 19th IEEE International Conference on Microelectronics, Cairo, Egypt, December 2007.
  15. Sanjay Burman, D. Mukhopadhyay and V. Kamakoti, LFSR based Stream Ciphers are Vulnerable to Power Attacks, Appeared in Proceedings of the INDOCRYPT, Lecture Notes in Computer Science (LNCS 4859), Chennai, India, December 2007, pp. 384-392.
  16. Saravanan, M., Ravindran, B., and Raman, S. (2007) "Legal Ontology for Query Enhancement". In the Proceedings of the Twentieth Annual Conference on Legal Knowledge and Information Systems(JURIX 2007), pp.171-172. IOS Press.
  17. Sarma, B.H.S. and Ravindran, B. (2007) "Intelligent Tutoring System using Reinforcement Learning to Teach Autistic Students". In the Proceedings of the Conference on Home/Community Oriented ICT for the Next Billion (HOIT 2007), pp. 65-78. Springer.
  18. Sriram, R. and Ravindran, B. (2007) "Homogeneous Hierarchical Composition of Areas in Multi-Robot Area Coverage". In the Proceedings of the Seventh Symposium on Abstraction, Approximation, and Reformulation (SARA 2007), pp. 300-313, LNAI 4612. Springer.
  19. Awasthi, P., Gagrani, A., and Ravindran, B. (2007) "Image Modeling using Tree Structured Conditional Random Fields". In the Proceedings of the Twentieth International Joint Conference on Artificial Intelligence (IJCAI 2007), pp. 2060-2065. AAAI Press.
  20. Narayanamurthy, S. M. and Ravindran, B. (2007) "Efficiently Exploiting Symmetries in Real Time Dynamic Programming". In the Proceedings of the Twentieth International Joint Conference on Artificial Intelligence (IJCAI 2007), pp. 2556-2561. AAAI Press.
  21. Ravindran, B., Barto, A. G., and Mathew, V. (2007) "Deictic Option Schemas". In the Proceedings of the Twentieth International Joint Conference on Artificial Intelligence (IJCAI 2007), pp. 1023-1028. AAAI Press.
  22. Jayarajan, D., Deodhare, D., Ravindran, B., and Sarkar, S. (2007) "Document Clustering using Lexical Chains". In the Proceedings of the Workshop on Text-Mining & Link-Analysis (TextLink 2007).
  23. Sriram, R. and Ravindran, B. (2007) "Profiling Pseudonet Architecture for Coordinating Mobile Robots". In the Proceedings of the Second IEEE International Conference on COMmunication System softWAre and MiddlewaRE (COMSWARE 2007). IEEE Press.
  24. Madhu Mutyam, Narayanan Vijaykrishnan: Working with process variation aware caches. DATE 2007: 1152-1157
  25. Madhu Mutyam: Selective shielding: a crosstalk-free bus encoding technique. ICCAD 2007: 618-621
  26. Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Variation Analysis of CAM Cells. ISQED 2007: 333-338
  27. Andrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin: Investigating Simple Low Latency Reliable Multiported Register Files. ISVLSI 2007: 375-382
  28. Nallamothu Satyanarayana, Madhu Mutyam, A. Vinaya Babu: Exploiting on-chip data behavior for delay minimization. SLIP 2007: 103-110