SHAKTI Processor Project
The SHAKTI processor project aims to build 6 variants of processors based on the RISC-V ISA from UC Berkeley (www.riscv.org). The project will develop a complete reference SoC for each family which will serve as an exemplar for that category of processor. While the cores and most of the SoC components (including bus and interconnect fabrics) will be in open source, some standard components like PCIe controller, DDR controller and PHY IP will be proprietary 3rd part IP.
All source will be licensed using a 3 part BSD license and will be royalty and patent free (as far as IIT-Madras is concerned, we will not assert any patents). While the primary focus is research, the SoCs are being designed to be competitive with commercial processors with respect to features, silicon area, power profile and frequency. This of course assumes that an optimal layout process is used to tape out our design. All FPGA data (Xilinx) will also be made available
While we do plan to tape out a few variants, given the foundry NDA requirements, we will not be able to publish any layout/backend data.
Students seeking internship/collaboration under this project are requested to fill this FORM
32-bit 3-8 stage in-order variant aimed at 50-250 Mhz microcontroller variants
Optional memory protection Very low power static design
Fault Tolerant variants for ISO26262 applications
IoT variants will have compressed/reduced ISA support
64-bit, 1-4 core, 5-8 stage out of order, aimed at 200-1Ghz industrial control / general purpose applications
Devices aimed at networking applications will have dual-quad issue support
Other features - shared L2 cache, AXI bus, threading support
Enhanced variants of the I-class processors aimed at general purpose compute, low end server and mobile applications
Enhancements over I class – large issue size, quad-threaded, up to 8 cores, freq up to 2.5 Ghz, optional NoC fabric
64-bit superscalar, multi-threaded variant for desktop/server applications.
1.2-3Ghz, 2-16 cores, crossbar/ring interconnect, segmented L3 cache
RapidIO based external cache coherent interconnect for multi-socket applications (up to 256 sockets)
Hybrid Memory Cube support
256/512 bit SIMD
Specialized variants with FUs for database acceleration, security acceleration.
Experimental variants will be used as test-bed for our Adaptive System Fabric project which aims to design a data-center architecture using NV RAM devices and unified interconnects for memory, storage and networking and leverages persistent memory techniques
64-bit in-order, multi-threaded, HPC variant with 32-100 cores
512 bit SIMD
Goal is 3-5 + Tflops (DP, sustained)
Experimental security oriented 64-bit variants with tagged ISA, single address space support, decoupling of protection from memory management.
We are also developing a processor to processor cache-coherent interconnect to allow building of multi-socket S class systems. The interconnect is based on the RapidIO interconnect. We are investigating a two tier scheme where a MOESI/MESIF style scheme is used for 2-8 socket systems anda directory based scheme for larger configurations (max 256 sockets)
The approach is to built optimal (high performance) building blocks that can be shared among the variants and then add variant specific blocks. The above variants are just canonical references and the Shakti family will see variants that will be hybrids.
When possible, we have also provided the Synopsys and Xilinx synthesis results for each module.
Final versions will contain the full BSV code, the generated Verilog code, testbenches, verification IP and FPGA support files.
The SHAKTI effort is part of a larger effort to build complte systems. As part of this effort, IIT-M is developing interconnects (optical and copper) based on Gen 3 (10/25G per lane) RapidIO and a scale-out SSD storage system called lightsor (see lightstor.org) based on this interconnect. The final goal is to build a fabric called Adaptive System fabric that will use a combination of Hybrid Memory Cubes and RapidIO that will unify support for compute, networking and storage.
The code repository is bitbucket.org/casl
Currently the RapidIO code and the storage controller code is available.